公开(公告)号：US5369049A

公开(公告)日：1994-11-29

申请号：US169873

申请日：1993-12-17

申请人： Joyce E. Acocella ,  Louis L. Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph F. Shepard

发明人： Joyce E. Acocella ,  Louis L. Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph F. Shepard

IPC分类号： H01L27/108 ,  H01L27/00 ,  H01L21/70

CPC分类号： H01L27/10829

摘要： A method of forming a MOS DRAM cell having a trench capacitor in which the strap connection to the trench capacitor, the source, drain, and isolation are all raised above the surface of the single crystal silicon includes the steps of forming the trench capacitors, depositing a blanket gate stack including the gate oxide and a set of gate layers, and then depositing isolation members in apertures etched in the gate stack using the gate oxide as an etch stop. The same sidewalls that are used to form an LDD source and drain form a self-aligned aperture for a surface strap that insulates the strap from misaligned portions of the gate stack.

摘要翻译： 一种形成具有沟槽电容器的MOS DRAM单元的方法，其中与沟槽电容器的带连接，源极，漏极和隔离都在单晶硅的表面上方升高，包括以下步骤：形成沟槽电容器， 包括栅极氧化物和一组栅极层的覆盖栅极堆叠，然后使用栅极氧化物作为蚀刻停止层，在隔离栅堆叠中蚀刻的孔中沉积隔离元件。 用于形成LDD源和漏极的相同侧壁形成用于将带与栅堆叠的未对准部分绝缘的表面带的自对准孔。

公开(公告)号：US5622881A

公开(公告)日：1997-04-22

申请号：US319393

申请日：1994-10-06

申请人： Joyce E. Acocella ,  Carol Galli ,  Louis Lu-Chen Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph F. Shepard

发明人： Joyce E. Acocella ,  Carol Galli ,  Louis Lu-Chen Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph F. Shepard

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C13/00

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11546 ,  Y10S148/117 ,  Y10S438/981

摘要： Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.

摘要翻译： 通过将浮置栅极结构限制在被薄氮化物层覆盖的隔离结构之间，可在电可编程存储器中实现提高的封装密度以及改进的性能和制造产量。 浮栅的限制是通过平面化，优选采用自限制化学/机械抛光工艺，覆盖覆盖隔离结构的氮化物层的表面来实现的。 然后可以在基本平坦的表面上形成栅极氧化物和控制电极连接，而不会损害器件必须承受编程的栅极氧化物的质量或击穿电压。 由于避免了形成这些连接的严格的拓扑结构，所以可能包括可能包括金属连接的低电阻连接的形成得到改进，并且允许将存储器单元的晶体管缩放到先前不可能的尺寸。

公开(公告)号：US4551906A

公开(公告)日：1985-11-12

申请号：US560629

申请日：1983-12-12

申请人： Seiki Ogura ,  Jacob Riseman ,  Nivo Rovedo ,  Joseph F. Shepard

发明人： Seiki Ogura ,  Jacob Riseman ,  Nivo Rovedo ,  Joseph F. Shepard

IPC分类号： H01L21/8222 ,  H01L21/28 ,  H01L21/331 ,  H01L21/336 ,  H01L27/06 ,  H01L27/082 ,  H01L29/73 ,  H01L21/265 ,  H01L21/225

CPC分类号： H01L29/6625 ,  H01L29/66272 ,  H01L29/66606

摘要： A semiconductor body having surface regions thereof isolated from other such regions by a pattern of dielectric isolation is provided. At least two narrow widths PN junction regions are located within at least one of the surface regions. Each PN junction has a width dimension substantially that of its electrical contact. Substantially vertical conformal conductive layers electrically ohmic contact each of the PN junction regions. The PN junction regions are the emitter and collector regions for a lateral bipolar transistor. A base PN junction region of an opposite conductivity is located between and contiguous to the emitter and the collector junctions. Substantially horizontal conductive layers are in electrical contact with an edge of each of the vertical conductive layers and separated from the surface regions by a first electrical insulating layer. A second insulating layer covers the conformal conductive layers. The horizontal conductive layer is patterned so as to have electrically separated conductive lines from one another. A third electrical insulating layer is located over the patterned horizontal conductive layers. An electrical contact is made to each of the horizontal conductive layers through an opening in the third electrical insulating layer which effectively makes contacts to the emitter and collector regions through the patterned horizontal conductive layers and the vertical conductive layers. An ohmic contact is made to the base region which is separated from the vertical conductive layers by the second insulating layer.

摘要翻译： 提供了具有通过介电隔离图案与其它这样的区域隔离的表面区域的半导体本体。 至少两个窄宽度PN结区域位于至少一个表面区域内。 每个PN结的宽度尺寸基本上是其电接触点。 基本上垂直的保形导电层电阻接触每个PN结区域。 PN结区域是用于横向双极晶体管的发射极和集电极区域。 具有相反电导率的基极PN结区域位于发射极和集电极结之间并且邻近发射极和集电极结。 基本上水平的导电层与每个垂直导电层的边缘电接触并且通过第一电绝缘层与表面区域分离。 第二绝缘层覆盖保形导电层。 将水平导电层图案化成具有彼此分离的导电线。 第三电绝缘层位于图案化的水平导电层上。 通过第三电绝缘层中的开口对每个水平导电层进行电接触，其有效地通过图案化的水平导电层和垂直导电层与发射极和集电极区域接触。 与通过第二绝缘层与垂直导电层分离的基极区域进行欧姆接触。

公开(公告)号：US4641170A

公开(公告)日：1987-02-03

申请号：US762669

申请日：1985-08-05

申请人： Seiki Ogura ,  Jacob Riseman ,  Nivo Rovedo ,  Joseph F. Shepard

发明人： Seiki Ogura ,  Jacob Riseman ,  Nivo Rovedo ,  Joseph F. Shepard

IPC分类号： H01L21/331 ,  H01L21/336 ,  H01L29/72

CPC分类号： H01L29/6625 ,  H01L29/66272 ,  H01L29/66606

摘要： An integrated circuit structure which includes small area lateral bipolar and method for making the same is described. A semiconductor body, such as a monocrystalline silicon wafer, having surface regions thereof isolated from other such regions by a pattern of dielectric isolation is provided. At least two narrow widths PN junction regions are located within at least one of the surface regions. Each PN junction has a width dimension substantially that of its electrical contact. Substantially vertical conformal conductive layers electrically ohmic contact each of the PN junction regions. The PN junction regions are the emitter and collector regions for a lateral bipolar transistor. A base PN junction base region of an opposite conductivity is located between and contiguous to the emitter and the collector junctions. Substantially horizontal conductive layers are in electrical contact with an edge of each of the vertical conductive layers and separated from the surface regions by a first electrical insulating layer. A second insulating layer covers the conformal conductive layers. The horizontal conductive layer is patterned so as to have electrically separated conductive lines from one another. A third electrical insulating layer is located over the patterned horizontal conductive layers. An electrical ohmic contact is made to each of the horizontal conductive layers through an opening in the third electrical insulating layer which effectively makes electrical contacts to the emitter and collector regions through the patterned horizontal conductive layers and the vertical conductive layers. An electrical ohmic contact is made to the centrally located base region which contact is separated from the vertical conductive layers by the second insulating layer.

摘要翻译： 描述了包括小面积横向双极的集成电路结构及其制造方法。 提供了半导体本体，例如单晶硅晶片，其表面区域通过介电隔离图案与其它这样的区域隔离。 至少两个窄宽度PN结区域位于至少一个表面区域内。 每个PN结的宽度尺寸基本上是其电接触点。 基本上垂直的保形导电层电阻接触每个PN结区域。 PN结区域是用于横向双极晶体管的发射极和集电极区域。 具有相反电导率的基极PN结基区位于发射极和集电极结之间并且与发射极和集电极结邻接。 基本上水平的导电层与每个垂直导电层的边缘电接触，并通过第一电绝缘层与表面区域分离。 第二绝缘层覆盖保形导电层。 将水平导电层图案化成具有彼此分离的导电线。 第三电绝缘层位于图案化的水平导电层上。 通过第三电绝缘层中的开口对每个水平导电层进行电欧姆接触，其有效地通过图案化的水平导电层和垂直导电层与发射极和集电极区域电接触。 对中心位置的基极区域进行电欧姆接触，该接触部分通过第二绝缘层与垂直导电层分离。

公开(公告)号：US4729006A

公开(公告)日：1988-03-01

申请号：US840180

申请日：1986-03-17

申请人： Anthony J. Dally ,  Seiki Ogura ,  Jacob Riseman ,  Nivo Rovedo

发明人： Anthony J. Dally ,  Seiki Ogura ,  Jacob Riseman ,  Nivo Rovedo

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L27/02 ,  H01L29/06 ,  H01L29/34 ,  H01L29/78

CPC分类号： H01L21/76224

摘要： A method for forming fully recessed (planar) isolation regions on a semiconductor for the manufacture of CMOS integrated circuits, and the resulting semiconductor structure, comprising in a P doped silicon substrate with mesas formed therein, forming low viscosity sidewall spacers of borosilicate glass in contact with the sidewalls of those mesas designated to have N-channel devices formed therein; then filling the trenches in the substrate adjacent to the mesas with TEOS; and heating the structure until the boron in the sidewall spacers diffuses into the sidewalls of the designated mesas to form channel stops. These sidewall spacers reduce the occurrence of cracks in the TEOS by relieving internal mechanical stress therein and permit the formation of channel stops via diffusion, thereby permitting mesa walls to be substantially vertical.

摘要翻译： 一种用于在用于制造CMOS集成电路的半导体上形成完全凹陷（平面）隔离区域的方法，所得到的半导体结构包括在其中形成有台面的P掺杂硅衬底中，形成接触的硼硅酸盐玻璃的低粘度侧壁间隔物 其中所述台面的侧壁被指定为在其中形成有N沟道器件; 然后用TEOS填充与台面相邻的基板中的沟槽; 并加热该结构直到侧壁间隔物中的硼扩散到指定台面的侧壁中以形成通道停止点。 这些侧壁间隔件通过减轻TEOS中的内部机械应力来减少TEOS中的裂纹的发生，并允许通过扩散形成通道停止，从而允许台面壁基本上垂直。

公开(公告)号：US4671851A

公开(公告)日：1987-06-09

申请号：US791861

申请日：1985-10-28

申请人： Klaus D. Beyer ,  James S. Makris ,  Eric Mendel ,  Karen A. Nummy ,  Seiki Ogura ,  Jacob Riseman ,  Nivo Rovedo

发明人： Klaus D. Beyer ,  James S. Makris ,  Eric Mendel ,  Karen A. Nummy ,  Seiki Ogura ,  Jacob Riseman ,  Nivo Rovedo

IPC分类号： H01L21/76 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763

CPC分类号： H01L21/763 ,  H01L21/31053 ,  H01L21/743 ,  H01L21/76202

摘要： A chemical-mechanical (chem-mech) method for removing SiO.sub.2 protuberances at the surface of a silicon chip, such protuberances including "bird's heads". A thin etch stop layer of Si.sub.3 N.sub.4 is deposited onto the wafer surface, which is then chem-mech polished with a SiO.sub.2 water based slurry. The Si.sub.3 N.sub.4 acts as a polishing or etch stop barrier layer only on the planar portions of the wafer surface. The portions of the Si.sub.3 N.sub.4 layer located on the top and at the sidewalls of the "bird's heads" and the underlying SiO.sub.2 protuberances are removed to provide a substantially planar integrated structure.

摘要翻译： 用于去除硅片表面的SiO 2突起的化学机械（化学机械）方法，包括“鸟头”的突起。 将Si 3 N 4的薄的蚀刻停止层沉积在晶片表面上，然后用SiO 2水基浆料进行化学研磨。 Si 3 N 4仅在晶片表面的平面部分上用作抛光或蚀刻阻挡层。 位于“鸟头”顶部和侧壁处的Si 3 N 4层的部分和下面的SiO 2突起被去除以提供基本平坦的整体结构。

公开(公告)号：US5892257A

公开(公告)日：1999-04-06

申请号：US708432

申请日：1996-09-05

申请人： Joyce Elizabeth Acocella ,  Carol Galli ,  Louis Lu-Chen Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph Francis Shepard

发明人： Joyce Elizabeth Acocella ,  Carol Galli ,  Louis Lu-Chen Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph Francis Shepard

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11546 ,  Y10S148/117 ,  Y10S438/981

摘要： Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.

摘要翻译： 通过将浮置栅极结构限制在被薄氮化物层覆盖的隔离结构之间，可在电可编程存储器中实现提高的封装密度以及改进的性能和制造产量。 浮栅的限制是通过平面化，优选采用自限制化学/机械抛光工艺，覆盖覆盖隔离结构的氮化物层的表面来实现的。 然后可以在基本平坦的表面上形成栅极氧化物和控制电极连接，而不会损害器件必须承受编程的栅极氧化物的质量或击穿电压。 由于避免了形成这些连接的严格的拓扑结构，所以可能包括可能包括金属连接的低电阻连接的形成得到改进，并且允许将存储器单元的晶体管缩放到先前不可能的尺寸。

公开(公告)号：US5541130A

公开(公告)日：1996-07-30

申请号：US477791

申请日：1995-06-07

申请人： Seiki Ogura ,  Nivo Rovedo ,  Robert C. Wong

发明人： Seiki Ogura ,  Nivo Rovedo ,  Robert C. Wong

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/115 ,  Y10S438/972

摘要： A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain region of each pair of adjacent memory array cells associated with the bit line. In one embodiment, multiple layers of polysilicon are utilized to form a control gate, a floating gate, a source and a drain. In another embodiment, multiple layers of polysilicon are utilized to form an auxiliary gate, a floating gate, a source and a drain. In both embodiments, the polysilicon layers self-aligned to substantially reduce polysilicon layer-overlap so as to minimize parasitic capacitances. Domino and Skippy Domino schemes are used to program and read the memory array cells. Programming may be implemented with channel hot-electron tunneling using relatively low programming voltages thereby realizing faster programming time and closer bit-line spacing.

摘要翻译： 一种用于制造高密度存储器阵列的方法。 将N型杂质注入p型衬底中以形成具有基本平坦轮廓的连续扩散轨道。 每个扩散轨定义相应的位线。 每个轨道限定与位线相关联的每对相邻存储器阵列单元的源极和漏极区域。 在一个实施例中，利用多层多晶硅来形成控制栅极，浮置栅极，源极和漏极。 在另一实施例中，利用多层多晶硅来形成辅助栅极，浮栅，源极和漏极。 在两个实施例中，多晶硅层自对准以显着减少多晶硅层重叠，从而使寄生电容最小化。 Domino和Skippy Domino方案用于对内存阵列单元进行编程和读取。 通过使用相对较低的编程电压的通道热电子隧穿可以实现编程，从而实现更快的编程时间和更靠近的位线间隔。

公开(公告)号：USH986H

公开(公告)日：1991-11-05

申请号：US363747

申请日：1989-06-09

申请人： Christopher F. Codella ,  Nivo Rovedo ,  Seiki Ogura

发明人： Christopher F. Codella ,  Nivo Rovedo ,  Seiki Ogura

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/66659 ,  H01L21/28132 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/7835

摘要： A field effect transistor of asymmetrical structure comprises: a semiconductor substrate of first conductivity type; source and drain regions of second conductivity type disposed in a surface of the substrate and spaced apart by a channel region; and a single, lightly doped extension of the drain region into the channel, the extension being of the second conductivity type and of a lower dopant concentration than the drain region. The transistor can further beneficially comprise a halo region of the first conductivity type in the substrate generally surrounding only the source region.

公开(公告)号：US4868135A

公开(公告)日：1989-09-19

申请号：US287945

申请日：1988-12-21

申请人： Seiki Ogura ,  Nivo Rovedo

发明人： Seiki Ogura ,  Nivo Rovedo

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/07

CPC分类号： H01L21/8249 ,  H01L27/0623 ,  H01L27/0711

摘要： A method for fabricating a Bi-CMOS device is disclosed herein, which device can include both vertical PNP and NPN components. The process steps include forming the reach-through N+ subcollector to the bipolar device without extra processing steps; combining into one mask the threshold adjust/well implants with self-aligned isolation leakage protection implants by using a self-aligned, removable oxide mask prior to field isolation; using a resist etch-back scheme to protect against emitter-to-base punch-through while self-aligning the pedestal and base; and also providing for the removal of the gate oxide at the emitter while maintaining it at the FET, without extra masks.The device incorporates similar structural featues between the bi-polar and FET devices. The NPN and pFET can share the same well and a P+ diffusion (the p+ extrinsic base is the same as the p+ source). Also, the pnp and nFET can share the same well and an n+ diffusion.