公开(公告)号：US4729006A

公开(公告)日：1988-03-01

申请号：US840180

申请日：1986-03-17

申请人： Anthony J. Dally ,  Seiki Ogura ,  Jacob Riseman ,  Nivo Rovedo

发明人： Anthony J. Dally ,  Seiki Ogura ,  Jacob Riseman ,  Nivo Rovedo

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L27/02 ,  H01L29/06 ,  H01L29/34 ,  H01L29/78

CPC分类号： H01L21/76224

摘要： A method for forming fully recessed (planar) isolation regions on a semiconductor for the manufacture of CMOS integrated circuits, and the resulting semiconductor structure, comprising in a P doped silicon substrate with mesas formed therein, forming low viscosity sidewall spacers of borosilicate glass in contact with the sidewalls of those mesas designated to have N-channel devices formed therein; then filling the trenches in the substrate adjacent to the mesas with TEOS; and heating the structure until the boron in the sidewall spacers diffuses into the sidewalls of the designated mesas to form channel stops. These sidewall spacers reduce the occurrence of cracks in the TEOS by relieving internal mechanical stress therein and permit the formation of channel stops via diffusion, thereby permitting mesa walls to be substantially vertical.

摘要翻译： 一种用于在用于制造CMOS集成电路的半导体上形成完全凹陷（平面）隔离区域的方法，所得到的半导体结构包括在其中形成有台面的P掺杂硅衬底中，形成接触的硼硅酸盐玻璃的低粘度侧壁间隔物 其中所述台面的侧壁被指定为在其中形成有N沟道器件; 然后用TEOS填充与台面相邻的基板中的沟槽; 并加热该结构直到侧壁间隔物中的硼扩散到指定台面的侧壁中以形成通道停止点。 这些侧壁间隔件通过减轻TEOS中的内部机械应力来减少TEOS中的裂纹的发生，并允许通过扩散形成通道停止，从而允许台面壁基本上垂直。

公开(公告)号：US4689113A

公开(公告)日：1987-08-25

申请号：US842576

申请日：1986-03-21

申请人： Karanam Balasubramanyam ,  Anthony J. Dally ,  Jacob Riseman ,  Seiki Ogura

发明人： Karanam Balasubramanyam ,  Anthony J. Dally ,  Jacob Riseman ,  Seiki Ogura

IPC分类号： H01L21/3205 ,  G03F7/09 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/768 ,  B44C1/22 ,  B29C37/00 ,  C03C15/00 ,  C23F1/02

CPC分类号： H01L21/0272 ,  G03F7/094 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/7688 ,  Y10S438/951 ,  Y10S438/963

摘要： Disclosed is a process of forming high density, planar, single- or multi-level wiring for a semiconductor integrated circuit chip. On the chip surface is provided a dual layer of an insulator and hardened photoresist having various sized openings (grooves for wiring and openings for contacts) therein in a pattern of the desired wiring. A conductive (e.g., metal) layer of a thickness equal to that of the insulator is deposited filling the grooves and contact openings. A sacrificial dual (lower and upper component) layer of (hardened) photoresist is formed filling the metal valleys and obtaining a substantially planar surface. The lower component layer is thin and conformal and has a higher etch rate than the upper component layer which is thick and nonconformal. By reactive ion etching the sacrificial layer is removed leaving resist plugs in the metal valleys. Using the plug as etch masks, the exposed metal is removed followed by removal of the remaining hardened photoresist layer and the plugs leaving a metal pattern coplanar with the insulator layer. This sequence of steps is repeated for multilevel wiring.When only narrow wiring is desired, a single photoresist layer is substituted for the dual photoresist sacrificial layer.

公开(公告)号：US5155572A

公开(公告)日：1992-10-13

申请号：US680490

申请日：1991-04-04

申请人： Dominique Bonneau ,  Myriam Combes ,  Anthony J. Dally ,  Pierre Mollier ,  Seiki Ogura ,  Pascal Tannhof

发明人： Dominique Bonneau ,  Myriam Combes ,  Anthony J. Dally ,  Pierre Mollier ,  Seiki Ogura ,  Pascal Tannhof

IPC分类号： H01L27/06 ,  H01L21/331 ,  H01L21/8249 ,  H01L29/08 ,  H01L29/73 ,  H01L29/732 ,  H01L29/74

CPC分类号： H01L29/74 ,  H01L29/0821

摘要： A vertical isolated-collector PNP transistor structure (58) comprises a P+ region (45), a N region (44) and a P- well region (46) which form the emitter, the base and the collector, respectively. The P- well region is enclosed in a N type pocket comprised of a N+ buried layer (48) and a N reach-through region (47) in contact therewith. The contact regions (46-1, 47-1) to the P- well region (46) and to the N reach-through region (47) are shorted to define a common collector contact (59). In addition, the thickness W of the P- well region (46) is so minimized to allow transistor action of the parasitic NPN transistor formed by N PNP base region (44), P- well region (46) and the N+ buried layer, (48) respectively as the collector, the base and the emitter of said PNP transistor. The PNP transistor structure (67) may be combined with a conventional NPN transistor structure (61).

摘要翻译： 垂直隔离集电极PNP晶体管结构（58）包括分别形成发射极，基极和集电极的P +区（45），N区（44）和P-阱区（46）。 P阱区被包围在与N +掩埋层（48）和N接触区域（47）组成的N型槽中。 到P阱区域（46）和N到达区域（47）的接触区域（46-1,47-1）被短路以限定公共集电极接触件（59）。 此外，P阱区域（46）的厚度W被最小化以允许由N PNP基区（44），P-阱区（46）和N +掩埋层形成的寄生NPN晶体管的晶体管作用， （48）分别作为所述PNP晶体管的集电极，基极和发射极。 PNP晶体管结构（67）可以与传统的NPN晶体管结构（61）组合。

公开(公告)号：US06531410B2

公开(公告)日：2003-03-11

申请号：US09795610

申请日：2001-02-27

申请人： Claude Louis Bertin ,  Anthony J. Dally ,  John Atkinson Fifield ,  John Jesse Higgins ,  Jack Allan Mandelman ,  William Robert Tonti ,  Nicholas Martin van Heel

发明人： Claude Louis Bertin ,  Anthony J. Dally ,  John Atkinson Fifield ,  John Jesse Higgins ,  Jack Allan Mandelman ,  William Robert Tonti ,  Nicholas Martin van Heel

IPC分类号： H01L2131

CPC分类号： H01L21/2822 ,  H01L21/2255 ,  H01L21/26506 ,  H01L21/26533 ,  H01L21/28238 ,  H01L21/823462 ,  H01L29/42368 ,  H01L29/511 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66583 ,  H01L29/66613 ,  H01L29/7834

摘要： Damascene or non-damascene processing when used with a method that includes (a) forming a mask having an opening therethrough on a structure, said opening having sidewalls; (b) implanting an inhibiting species into said structure through the opening so as to form an inhibiting region in said structure; and (c) growing a dielectric layer on the structure in said opening, wherein the inhibiting region partially inhibits growth of the dielectric layer is capable of forming a semiconductor structure, e.g., MOSFET or anti-fuse, including a dual thickness dielectric layer. Alternatively, the dual thickness dielectric can be formed by replacing the inhibiting species mentioned above with a dielectric growth enhancement species which forms an enhancing region in the structure which aids in the growth of the dielectric layer.

公开(公告)号：US07276775B2

公开(公告)日：2007-10-02

申请号：US10329593

申请日：2002-12-26

申请人： Claude Louis Bertin ,  Anthony J. Dally ,  John Atkinson Fifield ,  John Jesse Higgins ,  Jack Allan Mandelman ,  William Robert Tonti ,  Nicholas Martin van Heel

发明人： Claude Louis Bertin ,  Anthony J. Dally ,  John Atkinson Fifield ,  John Jesse Higgins ,  Jack Allan Mandelman ,  William Robert Tonti ,  Nicholas Martin van Heel

IPC分类号： H01L29/04 ,  H01L31/036 ,  H01L27/10 ,  H01L29/00

CPC分类号： H01L21/2822 ,  H01L21/2255 ,  H01L21/26506 ,  H01L21/26533 ,  H01L21/28238 ,  H01L21/823462 ,  H01L29/42368 ,  H01L29/511 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66583 ,  H01L29/66613 ,  H01L29/7834

摘要： Damascene or non-damascene processing when used with a method that includes (a) forming a mask having an opening therethrough on a structure, said opening having sidewalls; (b) implanting an inhibiting species into said structure through the opening so as to form an inhibiting region in said structure; and (c) growing a dielectric layer on the structure in said opening, wherein the inhibiting region partially inhibits growth of the dielectric layer is capable of forming a semiconductor structure, e.g., MOSFET or anti-fuse, including a dual thickness dielectric layer. Alternatively, the dual thickness dielectric can be formed by replacing the inhibiting species mentioned above with a dielectric growth enhancement species which forms an enhancing region in the structure which aids in the growth of the dielectric layer.

摘要翻译： 当与包括（a）在结构上形成具有开口的掩模的方法一起使用时，镶嵌或非镶嵌加工，所述开口具有侧壁; （b）通过开口将抑制物质注入所述结构中，以在所述结构中形成抑制区域; 和（c）在所述开口中的结构上生长电介质层，其中抑制区域部分抑制电介质层的生长能够形成半导体结构，例如包括双重厚度介电层的MOSFET或反熔丝。 或者，可以通过用有助于电介质层生长的结构中形成增强区的介电生长增强物种代替上述抑制物质来形成双重厚度电介质。