公开(公告)号：US20130256660A1

公开(公告)日：2013-10-03

申请号：US13685859

申请日：2012-11-27

Applicant: Kazuhide ABE ,  Atsuko IIDA ,  Kazuhiko ITAYA ,  Junji WADATSUMI ,  Shouhei KOUSAI

Inventor： Kazuhide ABE ,  Atsuko IIDA ,  Kazuhiko ITAYA ,  Junji WADATSUMI ,  Shouhei KOUSAI

IPC: H01L29/84

CPC classification number: H01L29/84 ,  H01L2924/1461 ,  H03H9/2405 ,  H03H2009/02314

Abstract: A semiconductor device according to an embodiment has: a semiconductor substrate; an acoustic resonator formed on the semiconductor substrate, having a semiconductor layer including impurity electrically isolated from the substrate by depletion layer and configured to resonate at a predetermined resonance frequency based on acoustic standing wave excited in the semiconductor layer; a temperature detector formed on the semiconductor substrate and configured to detect temperature of the semiconductor substrate; a calculating unit formed on the semiconductor substrate and configured to perform calculation of temperature compensation based on the temperature detected by the temperature detector, kind of the impurity and concentration of the impurity; and a controller formed on the semiconductor substrate and configured to control the resonance frequency based on a result of the calculation by the calculating unit.

Abstract translation: 根据实施例的半导体器件具有：半导体衬底; 形成在所述半导体衬底上的声谐振器，具有包括通过耗尽层与所述衬底电绝缘的杂质的半导体层，并且被配置为基于在所述半导体层中激发的声驻波以预定的谐振频率谐振; 温度检测器，形成在所述半导体衬底上，并被配置为检测所述半导体衬底的温度; 计算单元，其形成在所述半导体基板上，并且被配置为基于由所述温度检测器检测到的温度进行温度补偿的计算，所述杂质的种类和所述杂质的浓度; 以及控制器，其形成在所述半导体基板上，并且被配置为基于所述计算单元的计算结果来控制所述共振频率。

公开(公告)号：US20080258815A1

公开(公告)日：2008-10-23

申请号：US11871451

申请日：2007-10-12

Applicant: Kazuhide ABE ,  Tadahiro Sasaki ,  Kazuhiko Itaya ,  Hideyuki Funaki

Inventor： Kazuhide ABE ,  Tadahiro Sasaki ,  Kazuhiko Itaya ,  Hideyuki Funaki

IPC: H03F3/16

CPC classification number: H03F3/245 ,  H01L23/66 ,  H01L27/0207 ,  H01L2223/6644 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03F3/195 ,  H03F3/211 ,  H03F3/601 ,  H03F2200/366 ,  H03F2200/451 ,  H03F2203/21178 ,  H01L2924/00

Abstract: An object is to provide a high frequency power amplifier in which lowering of output power during operation is prevented, influence of thermal noise is suppressed, high frequency operation is stable, and long-term reliability is ensured. The high frequency power amplifier includes a plurality of transistors having gate electrodes, source regions and drain regions, the gate electrodes, source regions and drain regions being respectively connected in common, and a plurality of acoustic reflection layers being buried in portions of the semiconductor substrate, the portions being located between adjacent transistors, the acoustic reflection layers being disposed in a direction which is oblique to a length direction of the gate electrode.

Abstract translation: 本发明的目的是提供一种高频功率放大器，其中防止了操作期间输出功率的降低，热噪声的影响被抑制，高频操作稳定，并且确保了长期的可靠性。 高频功率放大器包括具有栅电极，源极区和漏极区的多个晶体管，栅电极，源极区和漏区共同分别连接，并且多个声反射层被埋在半导体衬底的一部分中 ，所述部分位于相邻的晶体管之间，声反射层沿与栅电极的长度方向倾斜的方向设置。

公开(公告)号：US20080206924A1

公开(公告)日：2008-08-28

申请号：US11963485

申请日：2007-12-21

Applicant: Kazuhide ABE

Inventor： Kazuhide ABE

IPC: H01L21/20

CPC classification number: H01L29/6606 ,  H01L21/0465

Abstract: According to the first aspect of the present invention, a method for fabricating a semiconductor device with a silicon carbide (SiC) film is comprised of a process to grow a silicon carbide film on a substrate; and a process to form a groove in the periphery of a region on the silicon carbide film in which crystal defects are aggregated.According to the second aspect of the present invention, a method for fabricating a semiconductor device with a silicon carbide (SiC) film is comprised of a process to grow a silicon carbide film on a substrate; and a process to form a groove on said silicon carbide film so that a region in which crystal defects are aggregated in said silicon carbide film is removed.

Abstract translation: 根据本发明的第一方面，一种制造具有碳化硅（SiC）膜的半导体器件的方法包括在衬底上生长碳化硅膜的工艺; 以及在晶圆缺陷聚集的碳化硅膜上的区域的周围形成槽的工序。 根据本发明的第二方面，制造具有碳化硅（SiC）膜的半导体器件的方法包括在衬底上生长碳化硅膜的工艺; 以及在所述碳化硅膜上形成凹槽的过程，从而去除在所述碳化硅膜中晶体缺陷聚集的区域。

公开(公告)号：US20130256864A1

公开(公告)日：2013-10-03

申请号：US13688823

申请日：2012-11-29

Applicant: Toshihiko NAGANO ,  Kazuhide ABE ,  Hiroshi YAMADA ,  Kazuhiko ITAYA ,  Taihei NAKADA

Inventor： Toshihiko NAGANO ,  Kazuhide ABE ,  Hiroshi YAMADA ,  Kazuhiko ITAYA ,  Taihei NAKADA

IPC: H01L23/48 ,  H01L21/78

CPC classification number: H01L23/48 ,  H01L21/78 ,  H01L23/055 ,  H01L23/10 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/13007 ,  H01L2224/13111 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/14181 ,  H01L2224/16235 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81205 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/81986 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1461 ,  H01L2924/1515 ,  H01L2924/15788 ,  H01L2924/16153 ,  H01L2224/81 ,  H01L2924/01079 ,  H01L2924/01014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor package according to embodiments includes: a semiconductor chip including a front electrode on a front surface thereof and a back electrode on a back surface thereof; a front-side cap portion including an air gap in a portion between the semiconductor chip and the front-side cap portion and a front-side penetrating electrode, and is positioned to face the front surface of the semiconductor chip; a back-side cap portion bonded with a first cap portion to hermetically seal the semiconductor chip, includes an air gap at least in a portion between the semiconductor chip and the back-side cap portion and a back-side penetrating electrode, and is positioned to face the back surface of the semiconductor chip; a front-side connecting portion which electrically connects the front electrode and the front-side penetrating electrode; and a back-side connecting portion which electrically connects the back electrode and the back-side penetrating electrode.

Abstract translation: 根据实施例的半导体封装包括：半导体芯片，其前表面包括前电极，背面具有背电极; 在半导体芯片和前侧盖部分之间的部分中包括气隙的前侧盖部分和前侧穿透电极，并且被定位成面对半导体芯片的前表面; 与第一帽部接合以密封半导体芯片的背面盖部分至少在半导体芯片和背面侧帽部分之间的部分和背面贯通电极之间包括气隙，并且位于 面对半导体芯片的背面; 电连接前电极和前侧穿透电极的前侧连接部; 以及将背面电极和背面贯通电极电连接的背面侧连接部。

公开(公告)号：US20090021140A1

公开(公告)日：2009-01-22

申请号：US12122472

申请日：2008-05-16

Applicant: Isao TAKASU ,  Yuko NOMURA ,  Tsuyoshi HIOKI ,  Isao AMEMIYA ,  Kazuhide ABE

Inventor： Isao TAKASU ,  Yuko NOMURA ,  Tsuyoshi HIOKI ,  Isao AMEMIYA ,  Kazuhide ABE

IPC: H01L21/00 ,  H01J1/62

CPC classification number: H01L33/54 ,  H01L33/46 ,  H01L33/507 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2933/0041 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of manufacturing a light emitting device. The method includes: mounting a light emitting chip on a substrate; forming a transparent resin portion and a phosphor layer by using a liquid droplet discharging apparatus, the transparent resin portion being formed in a shape of a dome and covering the light emitting chip to fill an exterior thereof on the substrate, a phosphor layer containing phosphor and being formed on an exterior of the transparent resin portion close to at least a top side thereof; and forming a reflecting layer at a position exterior of the transparent resin portion and the phosphor layer close to the substrate.

Abstract translation: 一种制造发光器件的方法。 该方法包括：将发光芯片安装在基板上; 通过使用液滴喷射装置形成透明树脂部分和荧光体层，所述透明树脂部分形成为圆顶形状并且覆盖所述发光芯片以将其外部填充在所述基板上，所述荧光体层包含磷光体和 形成在透明树脂部分的至少其顶侧附近的外部; 并且在透明树脂部分的外部和靠近基板的荧光体层的位置处形成反射层。

公开(公告)号：US20080061871A1

公开(公告)日：2008-03-13

申请号：US11687770

申请日：2007-03-19

Applicant: Kazuhide ABE ,  Tadahiro SASAKI ,  Kazuhiko ITAYA ,  Hideyuki FUNAKI

Inventor： Kazuhide ABE ,  Tadahiro SASAKI ,  Kazuhiko ITAYA ,  Hideyuki FUNAKI

IPC: H03F1/14

CPC classification number: H03F3/2176 ,  H03F1/02 ,  H03F3/245 ,  H03F2200/366 ,  H03F2200/391 ,  H03F2203/21178 ,  H03G1/0088

Abstract: A power amplifier includes: a plurality of field effect transistors connected in parallel and each having a first and second ends, the first end being connected to ground; an amplifying unit which includes at least one of an inductor, a capacitor and a band pass filter and has a third and fourth ends, the third end being connected to the second ends of the field effect transistors, and the fourth end outputting an amplified output signal; and an amplitude controller which sends control signals respectively to gates of the field effect transistors to turn on or off the field effect transistors based on an address signal for performing selection on the field effect transistors and a clock signal. Channel widths of the field effect transistors are different from each other.

Abstract translation: 功率放大器包括：多个并联连接的场效应晶体管，每个具有第一和第二端，所述第一端连接到地; 放大单元，其包括电感器，电容器和带通滤波器中的至少一个，并具有第三和第四端，第三端连接到场效应晶体管的第二端，第四端输出放大的输出 信号; 以及幅度控制器，其基于用于对场效应晶体管进行选择的地址信号和时钟信号，分别向场效应晶体管的栅极发送控制信号以导通或关闭场效应晶体管。 场效应晶体管的沟道宽度彼此不同。

公开(公告)号：US20120241877A1

公开(公告)日：2012-09-27

申请号：US13220116

申请日：2011-08-29

Applicant: Kazuhide ABE ,  Tadahiro Sasaki ,  Atsuko Iida ,  Kazuhiko Itaya ,  Takashi Kawakubo

Inventor： Kazuhide ABE ,  Tadahiro Sasaki ,  Atsuko Iida ,  Kazuhiko Itaya ,  Takashi Kawakubo

IPC: H01L29/84

CPC classification number: H03J3/20 ,  H03B5/326 ,  H03H9/02566

Abstract: According to one embodiment, an acoustic semiconductor device includes an element unit, and a first terminal. The element unit includes an acoustic resonance unit. The acoustic resonance unit includes a semiconductor crystal. An acoustic standing wave is excitable in the acoustic resonance unit and is configured to be synchronously coupled with electric charge density within at least one portion of the semiconductor crystal via deformation-potential coupling effect. The first terminal is electrically connected to the element unit. At least one selected from outputting and inputting an electrical signal is implementable via the first terminal. The electrical signal is coupled with the electric charge density. The outputting the electrical signal is from the acoustic resonance unit, and the inputting the electrical signal is into the acoustic resonance unit.

Abstract translation: 根据一个实施例，声学半导体器件包括元件单元和第一端子。 元件单元包括声共振单元。 声共振单元包括半导体晶体。 声驻波在声共振单元中是可兴奋的，并且被配置为通过变形电势耦合效应与半导体晶体的至少一部分内的电荷密度同步耦合。 第一端子电连接到元件单元。 从输出和输入电信号中选出的至少一个可经由第一终端实现。 电信号与电荷密度耦合。 输出电信号来自声共振单元，并且输入电信号进入声共振单元。

公开(公告)号：US20120235246A1

公开(公告)日：2012-09-20

申请号：US13425735

申请日：2012-03-21

Applicant: Kazuhide ABE ,  Tadahiro Sasaki ,  Kazuhiko Itaya

Inventor： Kazuhide ABE ,  Tadahiro Sasaki ,  Kazuhiko Itaya

IPC: H01L27/088

CPC classification number: H03F1/02 ,  H01L27/105 ,  H03F1/32 ,  H03F3/211 ,  H03F2200/432

Abstract: One embodiment of a semiconductor device provided with a semiconductor substrate, a device region formed on the semiconductor substrate, a device isolation region, which encloses the device region, a plurality of first gate electrodes arranged so as to be parallel to each other on the device region and electrically connected to each other, and a plurality of second gate electrodes arranged so as to be parallel to a plurality of first gate electrodes on the device region and electrically connected to each other, wherein the first gate electrode is arranged so as to be interposed between the second gate electrodes, a gate width of the first gate electrode is smaller than the gate width of the second gate electrode, and a DC bias voltage higher than that of the second gate electrode is applied to the first gate electrode.

Abstract translation: 设置有半导体衬底的半导体器件的一个实施例，形成在半导体衬底上的器件区域，封装器件区域的器件隔离区域，在器件上彼此平行布置的多个第一栅极电极 并且彼此电连接;以及多个第二栅电极，其被布置成与所述器件区域上的多个第一栅极平行并且彼此电连接，其中所述第一栅电极被布置为 插入在第二栅电极之间，第一栅电极的栅极宽度小于第二栅电极的栅极宽度，并且将高于第二栅电极的直流偏置电压施加到第一栅电极。

公开(公告)号：US20090243725A1

公开(公告)日：2009-10-01

申请号：US12409926

申请日：2009-03-24

Applicant: Kazuhide ABE ,  Tadahiro Sasaki ,  Kazuhiko Itaya

Inventor： Kazuhide ABE ,  Tadahiro Sasaki ,  Kazuhiko Itaya

IPC: H03F3/185 ,  H01L25/065

CPC classification number: H03F3/195 ,  H01L23/585 ,  H01L23/66 ,  H01L29/0657 ,  H01L29/41758 ,  H01L29/4238 ,  H01L2223/6644 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a first transistor unit including first field effect transistors with first gate electrodes electrically connected together, first sources electrically connected together, and first drains electrically connected together, the first gate electrodes being electrically connected to the first drains, a second transistor unit including second field effect transistors with second gate electrodes electrically connected together, second sources electrically connected together, and second drains electrically connected together, the second gate electrodes being electrically connected to the first gate electrodes, and dummy gate electrodes electrically isolated from the first gate electrodes and the second gate electrodes. The first gate electrodes, the second gate electrodes, and the dummy gate electrodes are arranged parallel to one another, and at least one dummy gate electrode is located between any one of the first gate electrodes and any one of the second gate electrodes.

Abstract translation: 半导体器件包括第一晶体管单元，其包括第一场效应晶体管，第一栅电极电连接在一起，电连接在一起的第一源和电连接在一起的第一漏极，第一栅电极电连接到第一漏极，第二晶体管单元 包括第二场效应晶体管，其中第二栅电极电连接在一起，第二源电连接在一起，第二漏极电连接在一起，第二栅电极电连接到第一栅电极，以及虚栅极与第一栅电极电隔离 和第二栅电极。 第一栅电极，第二栅电极和伪栅极彼此平行布置，并且至少一个虚拟栅电极位于第一栅极电极和第二栅极电极中的任一个之间。