公开(公告)号：US20090081870A1

公开(公告)日：2009-03-26

申请号：US12325670

申请日：2008-12-01

申请人： Toshiyuki Takewaki ,  Kazuyoshi Ueno

发明人： Toshiyuki Takewaki ,  Kazuyoshi Ueno

IPC分类号： H01L21/44

CPC分类号： H01L23/53238 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76877 ,  H01L2924/0002 ,  Y10S438/978 ,  H01L2924/00

摘要： In a semiconductor device, an insulating interlayer is provided above a semiconductor substrate, and a plurality of first wiring layers and a plurality of second wiring layers are formed in the insulating interlayer. The first wiring layers are substantially composed of copper, and are arranged in parallel at a large pitch. The second wiring layers are substantially composed of copper, and are arranged in parallel at a small pitch. A first metal capping layer is formed on each of the first wiring layers, and a second metal capping layer is formed on each of the second wiring layers. The second metal capping layer has a smaller thickness than that of the first metal capping layer.

摘要翻译： 在半导体装置中，在半导体基板的上方设置绝缘中间层，在绝缘中间层中形成有多个第一布线层和多​​个第二布线层。 第一布线层基本上由铜组成，并以大间距平行布置。 第二布线层基本上由铜组成，并以小的间距平行布置。 第一金属覆盖层形成在每个第一布线层上，第二金属覆盖层形成在每个第二布线层上。 第二金属覆盖层的厚度小于第一金属覆盖层的厚度。

公开(公告)号：US20070245828A1

公开(公告)日：2007-10-25

申请号：US11640169

申请日：2006-12-18

申请人： Takamasa Nakajima ,  Kazuki Tsuda ,  Zenji Sakai ,  Kazuyoshi Ueno ,  Masakazu Shirahoshi ,  Koji Kawata ,  Yoshikado Yamauchi

发明人： Takamasa Nakajima ,  Kazuki Tsuda ,  Zenji Sakai ,  Kazuyoshi Ueno ,  Masakazu Shirahoshi ,  Koji Kawata ,  Yoshikado Yamauchi

IPC分类号： G01H11/00

CPC分类号： G01M7/02 ,  G01M7/022

摘要： Disclosed is a vibration test method for evaluating the vibration resistance of a specimen, comprising a test specification setting step (S10) of determining reference vibration conditions for the specimen based on transport conditions during actual transportation; a reference value attainment step (S20) of calculating an amplitude level and a reference accumulated fatigue value of the specimen under the reference vibration conditions; a test condition determination step (S30) of determining test vibration conditions and a test time based on an allowable amplification factor of the amplitude level and a desired vibration time, so that an accumulated fatigue value which is calculated from the vibration detection value of the specimen satisfies the reference accumulated fatigue value; and a vibration-imparting step (S40) of vibrating the specimen based on the test vibration conditions and the test time. In accordance with the vibration test method, a vibration test that conforms to the actual transportation environment can be readily performed with high accuracy.

摘要翻译： 公开了一种用于评价试样的抗振性的振动试验方法，其特征在于，包括根据实际运送中的运送条件来确定试样的基准振动条件的试验规格设定步骤（S10） 在参考振动条件下计算样本的振幅水平和基准累积疲劳值的基准值达到步骤（S20） 根据振幅水平的允许放大系数和期望的振动时间来确定测试振动条件和测试时间的测试条件确定步骤（S30），从而根据振幅检测值计算的累积疲劳值 试样满足参考累积疲劳值; 以及基于测试振动条件和测试时间使样本振动的振动赋予步骤（S40）。 根据振动试验方法，可以容易地以高精度进行符合实际运输环境的振动试验。

公开(公告)号：US06680247B2

公开(公告)日：2004-01-20

申请号：US10004859

申请日：2001-12-07

申请人： Kazuyoshi Ueno

发明人： Kazuyoshi Ueno

IPC分类号： H01L214763

CPC分类号： H01L21/76843 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76844

摘要： The manufacturing method of a semiconductor device includes a step of forming a lower wiring on a semiconductor substrate, a step of forming a layer insulating film on the lower wiring, a step of forming an opening that exposes the lower wiring by removing a part of the layer insulating film, a step of forming a barrier film in the opening and a step of forming an upper wiring in the opening, where the lower wiring and the upper wiring are copper including wirings composed of copper or a copper alloy, the barrier film covers the bottom face and the side face of the opening, and the barrier film on the bottom face of the opening is formed so as to have its thickness to be less than twice the diffusion length of the copper atoms in the barrier film.

摘要翻译： 半导体器件的制造方法包括在半导体衬底上形成下布线的步骤，在下布线上形成层绝缘膜的步骤，形成通过去除部分 在开口中形成阻挡膜的步骤以及在开口中形成上布线的步骤，其中下布线和上布线为铜，包括由铜或铜合金构成的布线，阻挡膜覆盖 开口的底面和侧面，开口的底面上的阻挡膜形成为具有小于阻挡膜中铜原子的扩散长度的两倍的厚度。

公开(公告)号：US06670270B1

公开(公告)日：2003-12-30

申请号：US09273627

申请日：1999-03-23

申请人： Kazuyoshi Ueno

发明人： Kazuyoshi Ueno

IPC分类号： H01L2100

CPC分类号： H01L21/28556 ,  C23C16/18 ,  C23C16/44 ,  C23C16/4585 ,  H01L21/67103 ,  H01L21/68721 ,  H01L21/76877

摘要： A semiconductor device manufacturing apparatus which uses a thermal CVD reaction to deposit a film onto a substrate has a ring with an electrode terminal that makes contact with either the substrate or the deposited film thereon, a power supply that applies a current or a potential to this electrode terminal of the ring, and a piston cylinder mechanism for moving the ring up and down, so as to cause its electrode terminal to make and break contact with the substrate or deposited film thereon.

公开(公告)号：US20050087138A1

公开(公告)日：2005-04-28

申请号：US10626233

申请日：2003-07-24

申请人： Kazuyoshi Ueno

发明人： Kazuyoshi Ueno

IPC分类号： H01L21/31 ,  C23C16/18 ,  C23C16/44 ,  C23C16/458 ,  C23C16/50 ,  C23C16/52 ,  H01L21/205 ,  H01L21/285 ,  C23C16/00

CPC分类号： H01L21/28556 ,  C23C16/18 ,  C23C16/44 ,  C23C16/4585 ,  H01L21/67103 ,  H01L21/68721 ,  H01L21/76877

摘要： A semiconductor device manufacturing apparatus which uses a thermal CVD reaction to deposit a film onto a substrate has a ring with an electrode terminal that makes contact with either the substrate or the deposited film thereon, a power supply that applies a current or a potential to this electrode terminal of the ring, and a piston cylinder mechanism for moving the ring up and down, so as to cause its electrode terminal to make and break contact with the substrate or deposited film thereon.

摘要翻译： 使用热CVD反应将膜沉积在基板上的半导体器件制造装置具有与其上的基板或沉积膜接触的电极端子的环，向其施加电流或电位的电源 所述环的电极端子和用于使所述环上下移动的活塞缸机构，以使其电极端子与其上的基板或沉积膜形成和断开接触。

公开(公告)号：US06391168B1

公开(公告)日：2002-05-21

申请号：US09542338

申请日：2000-04-05

申请人： Kazuyoshi Ueno

发明人： Kazuyoshi Ueno

IPC分类号： C25B900

CPC分类号： C25D17/007 ,  C25D7/123 ,  C25D17/001 ,  C25D17/02 ,  Y10S204/07

摘要： In the plating solution in the plating bath, a wafer and an anode electrode are opposed to each other, between which is interposed a disk-shaped auxiliary electrode having a diameter smaller than that of the wafer. This auxiliary electrode has a plurality of holes formed therein. Through these holes, the plating solution is uniformly supplied to between the wafer and the anode electrode. The auxiliary electrode is supplied with the same positive potential as that of the anode electrode. This forms electric lines of force directed from the auxiliary electrode and the anode electrode to the wafer. The closer provision of the anode electrode (the auxiliary electrode) compensates a drop in current density on the wafer resulting from the potential drop at the portion far from cathode terminals.

摘要翻译： 在电镀液中的镀液中，晶片和阳极彼此相对，在其间插入直径小于晶片直径的盘形辅助电极。 该辅助电极在其中形成有多个孔。 通过这些孔，将电镀溶液均匀地供给到晶片和阳极电极之间。 辅助电极被提供与阳极电极相同的正电位。 这形成从辅助电极和阳极电极引导到晶片的电力线。 阳极电极（辅助电极）的更靠近的设置补偿由远离阴极端子的部分的电位降引起的晶片上的电流密度下降。

公开(公告)号：US06268090B1

公开(公告)日：2001-07-31

申请号：US09512352

申请日：2000-02-24

申请人： Yoshihisa Matsubara ,  Kazumi Sugai ,  Nobukazu Ito ,  Kazuyoshi Ueno

发明人： Yoshihisa Matsubara ,  Kazumi Sugai ,  Nobukazu Ito ,  Kazuyoshi Ueno

IPC分类号： G03F900

CPC分类号： H01L21/76873 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a process for manufacturing a semiconductor device where a plurality of wafers are formed on a single wafer, comprising the steps of forming a groove pattern in an insulating layer on a wafer; forming a seed metal layer in the groove by spattering; depositing an interconnection metal layer on the seed metal layer by electrolytic plating; and then flattering the wafer to the surface of the insulating layer, during forming the groove pattern in the insulating layer, the groove pattern is formed in the area on the wafer where devices can be taken while forming a dummy pattern up to 30 &mgr;m long in the wafer periphery where devices cannot be taken, to prevent the interconnection metal layer from being peeled in the wafer periphery.

公开(公告)号：US06245676B1

公开(公告)日：2001-06-12

申请号：US09255562

申请日：1999-02-22

申请人： Kazuyoshi Ueno

发明人： Kazuyoshi Ueno

IPC分类号： H01L2144

CPC分类号： H01L21/76873 ,  C25D5/18 ,  C25D7/123 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877

摘要： The flexibility of a wiring design is improved by preventing any erosion from happening upon forming a buried wiring. An interlayer insulating film is formed on a silicon substrate, and then trenches are formed in the interlayer insulating film. Thereafter, the barrier layer is deposited on side surfaces and a bottom surface in the trenches and on an entire area on the interlayer insulating film, and a copper seed layer is formed over an entire area on the barrier layer. Fountain plating is performed using the copper seed layer as an electrode to deposit the copper plated layer on the trenches and on a peripheral area of the same the copper plated layer buries the trenches and has a protruded configuration. Thereafter, the surface of the copper plated layer is polished with a CMP method until the interlayer insulating film is exposed to form a buried wiring.

摘要翻译： 通过防止在形成掩埋布线时发生侵蚀，可以提高布线设计的灵活性。 在硅衬底上形成层间绝缘膜，然后在层间绝缘膜中形成沟槽。 此后，阻挡层沉积在沟槽中的侧表面和底表面以及层间绝缘膜上的整个区域上，并且在阻挡层上的整个区域上形成铜籽晶层。 使用铜种子层作为电极进行喷镀，以将铜镀层沉积在沟槽上，并且在其周边区域上，镀铜层埋入沟槽并具有突出构型。 此后，用CMP法研磨镀铜层的表面，直到层间绝缘膜露出来形成掩埋布线。

公开(公告)号：US5696017A

公开(公告)日：1997-12-09

申请号：US363883

申请日：1994-12-27

申请人： Kazuyoshi Ueno

发明人： Kazuyoshi Ueno

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10852 ,  H01L28/40

摘要： A semiconductor integrated circuit device with a capacitor structure having a large capacitance per unit surface is disclosed, wherein a contact hole is formed in an insulator layer, a metal electrode with or without a rugged surface is formed in the contact hole by an ion beam vapor deposition of metal, and a capacitor insulator layer is formed on a surface of the metal electrode. The metal electrode is integral with a contact metal. The capacitor structure comprises the metal electrode integral with the contact metal and the capacitor insulator layer which are buried in the contact hole. The device is improved in planarization, reduction of parasitic resistance, maintenance of capacitance and mass production ability.

摘要翻译： 公开了一种具有每单位表面电容大的电容器结构的半导体集成电路器件，其中在绝缘体层中形成接触孔，通过离子束蒸气在接触孔中形成具有或不具有粗糙表面的金属电极 在金属电极的表面上形成金属的沉积和电容器绝缘体层。 金属电极与接触金属是一体的。 电容器结构包括与接触金属一体的金属电极和埋在接触孔中的电容器绝缘体层。 该器件的平面化改善，寄生电阻降低，电容维持和量产能力。

公开(公告)号：US08784931B2

公开(公告)日：2014-07-22

申请号：US12565448

申请日：2009-09-23

申请人： Kazuyoshi Ueno ,  Tetsuya Osaka ,  Nao Takano

发明人： Kazuyoshi Ueno ,  Tetsuya Osaka ,  Nao Takano

IPC分类号： H05K1/09 ,  B05D5/12

CPC分类号： C23C18/1893 ,  C23C18/1651 ,  C25D7/12 ,  H01L21/288 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76874 ,  Y10T428/24917 ,  Y10T428/24926 ,  Y10T428/31663

摘要： A method of manufacturing ULSI wiring in which wiring layers are separately formed via a diffusion prevention layer and an insulating interlayer portion made of SiO2. The method comprises the steps of treating, with a silane compound, a SiO2 surface of the insulating interlayer portion on which the diffusion layer is to be formed, performing catalyzation with an aqueous solution containing a palladium compound, forming the diffusion prevention layer by electroless plating, and then forming the wiring layer on this diffusion prevention layer. A capping layer may be formed on the wiring layer by electroless plating. Consequently, a diffusion prevention layer having good adhesive properties can be formed through a simple wet process, and, the wiring layer can directly be formed on this diffusion prevention layer by a wet process. The capping layer can also be directly formed on the wiring layer by electroless plating.

摘要翻译： 一种制造ULSI布线的方法，其中布线层经由扩散防止层和由SiO 2制成的绝缘夹层部分分别形成。 该方法包括以下步骤：用硅烷化合物处理要形成扩散层的绝缘层间部分的SiO 2表面，用含有钯化合物的水溶液进行催化，通过化学镀形成扩散防止层 ，然后在该扩散防止层上形成布线层。 可以通过无电解电镀在布线层上形成覆盖层。 因此，通过简单的湿法可以形成具有良好粘合性的扩散防止层，并且可以通过湿法直接在该扩散防止层上形成布线层。 覆盖层也可以通过无电镀直接形成在布线层上。