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    Methods of forming integrated circuit devices with metal-insulator-metal capacitors
    1.
    发明申请
    Methods of forming integrated circuit devices with metal-insulator-metal capacitors 审中-公开
    用金属 - 绝缘体 - 金属电容器形成集成电路器件的方法

    公开(公告)号：US20060060907A1

    公开(公告)日：2006-03-23

    申请号：US11273505

    申请日：2005-11-14

    申请人： Ki-Chul Kim ,  Young-Sun Kim ,  Gab-Jin Nam ,  Sung-Tae Kim ,  Thomas Kwon ,  Han-Mei Choi ,  Jae-Soon Lim

    发明人： Ki-Chul Kim ,  Young-Sun Kim ,  Gab-Jin Nam ,  Sung-Tae Kim ,  Thomas Kwon ,  Han-Mei Choi ,  Jae-Soon Lim

    IPC分类号： H01L27/108

    CPC分类号： H01L21/32051 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/91

    摘要： A conductive contact plug extends through an opening in the dielectric layer to contact the substrate and includes a widened pad portion extending onto the dielectric layer adjacent the opening. An ohmic pattern is disposed on the pad portion of the plug, and a barrier pattern is disposed on the ohmic pattern. A concave first capacitor electrode is disposed on the barrier pattern and defines a cavity opening away from the substrate. A capacitor dielectric layer conforms to a surface of the first capacitor electrode and a second capacitor electrode is disposed on the capacitor dielectric layer opposite the first capacitor electrode. Sidewalls of the ohmic pattern, the barrier pattern and the pad portion of the contact plug may be substantially coplanar, and the device may further include an etch stopper layer conforming to at least sidewalls of the ohmic pattern, the barrier pattern and the pad portion of the contact plug. Related fabrication methods are described.

    摘要翻译： 导电接触插塞延伸穿过电介质层中的开口以接触衬底并且包括延伸到邻近开口的电介质层上的加宽焊盘部分。 欧姆图案设置在插头的焊盘部分上，并且阻挡图案设置在欧姆图案上。 凹陷的第一电容器电极设置在阻挡图案上并且限定了远离基板的空腔。 电容器电介质层符合第一电容器电极的表面，并且第二电容器电极设置在与第一电容器电极相对的电容器电介质层上。 欧姆图案的侧壁，接触塞的阻挡图案和焊盘部分可以是基本上共面的，并且该器件还可以包括符合至少欧姆图案的侧壁，阻挡图案和焊盘部分的蚀刻停止层 接触插头。 描述相关的制造方法。

    Integrated circuit devices with metal-insulator-metal capacitors
    2.
    发明授权
    Integrated circuit devices with metal-insulator-metal capacitors 有权
    具有金属 - 绝缘体 - 金属电容器的集成电路器件

    公开(公告)号：US06992346B2

    公开(公告)日：2006-01-31

    申请号：US10807000

    申请日：2004-03-23

    申请人： Ki-Chul Kim ,  Young-Sun Kim ,  Gab-Jin Nam ,  Sung-Tae Kim ,  Thomas Jongwan Kwon ,  Han-Mei Choi ,  Jae-Soon Lim

    发明人： Ki-Chul Kim ,  Young-Sun Kim ,  Gab-Jin Nam ,  Sung-Tae Kim ,  Thomas Jongwan Kwon ,  Han-Mei Choi ,  Jae-Soon Lim

    IPC分类号： H01L29/096

    CPC分类号： H01L21/32051 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/91

    摘要： A conductive contact plug extends through an opening in the dielectric layer to contact the substrate and includes a widened pad portion extending onto the dielectric layer adjacent the opening. An ohmic pattern is disposed on the pad portion of the plug, and a barrier pattern is disposed on the ohmic pattern. A concave first capacitor electrode is disposed on the barrier pattern and defines a cavity opening away from the substrate. A capacitor dielectric layer conforms to a surface of the first capacitor electrode and a second capacitor electrode is disposed on the capacitor dielectric layer opposite the first capacitor electrode. Sidewalls of the ohmic pattern, the barrier pattern and the pad portion of the contact plug may be substantially coplanar, and the device may further include an etch stopper layer conforming to at least sidewalls of the ohmic pattern, the barrier pattern and the pad portion of the contact plug. Related fabrication methods are described.

    摘要翻译： 导电接触插塞延伸穿过电介质层中的开口以接触衬底并且包括延伸到邻近开口的电介质层上的加宽焊盘部分。 欧姆图案设置在插头的焊盘部分上，并且阻挡图案设置在欧姆图案上。 凹陷的第一电容器电极设置在阻挡图案上并且限定了远离基板的空腔。 电容器电介质层符合第一电容器电极的表面，并且第二电容器电极设置在与第一电容器电极相对的电容器电介质层上。 欧姆图案的侧壁，接触塞的阻挡图案和焊盘部分可以是基本上共面的，并且该器件还可以包括符合至少欧姆图案的侧壁，阻挡图案和焊盘部分的蚀刻停止层 接触插头。 描述相关的制造方法。

    Semiconductor memory device and method of manufacturing the semiconductor memory device
    9.
    发明申请
    Semiconductor memory device and method of manufacturing the semiconductor memory device 有权
    半导体存储器件及半导体存储器件的制造方法

    公开(公告)号：US20060138523A1

    公开(公告)日：2006-06-29

    申请号：US11311143

    申请日：2005-12-20

    申请人： Jong-Cheol Lee ,  Jae-Hyoung Choi ,  Han-Mei Choi ,  Gab-Jin Nam ,  Young-Sun Kim

    发明人： Jong-Cheol Lee ,  Jae-Hyoung Choi ,  Han-Mei Choi ,  Gab-Jin Nam ,  Young-Sun Kim

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/513 ,  H01L29/7881

    摘要： Example embodiments of the present invention disclose a non-volatile semiconductor memory device, which may include a dielectric layer having an enhanced dielectric constant. A tunnel oxide layer pattern and a floating gate may be sequentially formed on a substrate. A dielectric layer pattern including metal oxide doped with Group III transition metals may be formed on the floating gate using a pulsed laser deposition process. The dielectric layer pattern having an increased dielectric constant may be formed of metal oxide doped with a transition metal such as scandium, yttrium, or lanthanum.

    摘要翻译： 本发明的示例实施例公开了一种非易失性半导体存储器件，其可以包括具有增强介电常数的介电层。 可以在衬底上依次形成隧道氧化物层图案和浮栅。 可以使用脉冲激光沉积工艺在浮栅上形成包括掺杂有III族过渡金属的金属氧化物的电介质层图案。 具有增加的介电常数的电介质层图案可以由掺杂有过渡金属如钪，钇或镧的金属氧化物形成。

    Semiconductor memory device and method of manufacturing the semiconductor memory device
    10.
    发明授权
    Semiconductor memory device and method of manufacturing the semiconductor memory device 有权
    半导体存储器件及半导体存储器件的制造方法

    公开(公告)号：US07338863B2

    公开(公告)日：2008-03-04

    申请号：US11311143

    申请日：2005-12-20

    申请人： Jong-Cheol Lee ,  Jae-Hyoung Choi ,  Han-Mei Choi ,  Gab-Jin Nam ,  Young-Sun Kim

    发明人： Jong-Cheol Lee ,  Jae-Hyoung Choi ,  Han-Mei Choi ,  Gab-Jin Nam ,  Young-Sun Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/513 ,  H01L29/7881

    摘要： Example embodiments of the present invention disclose a non-volatile semiconductor memory device, which may include a dielectric layer having an enhanced dielectric constant. A tunnel oxide layer pattern and a floating gate may be sequentially formed on a substrate. A dielectric layer pattern including metal oxide doped with Group III transition metals may be formed on the floating gate using a pulsed laser deposition process. The dielectric layer pattern having an increased dielectric constant may be formed of metal oxide doped with a transition metal such as scandium, yttrium, or lanthanum.

    摘要翻译： 本发明的示例实施例公开了一种非易失性半导体存储器件，其可以包括具有增强介电常数的介电层。 可以在衬底上依次形成隧道氧化物层图案和浮栅。 可以使用脉冲激光沉积工艺在浮栅上形成包括掺杂有III族过渡金属的金属氧化物的电介质层图案。 具有增加的介电常数的电介质层图案可以由掺杂有过渡金属如钪，钇或镧的金属氧化物形成。