公开(公告)号：US20110254084A1

公开(公告)日：2011-10-20

申请号：US13039089

申请日：2011-03-02

申请人： Kyle Terrill ,  Yuming Bai ,  Deva Pattanayak ,  Zhiyun Luo

发明人： Kyle Terrill ,  Yuming Bai ,  Deva Pattanayak ,  Zhiyun Luo

IPC分类号： H01L29/78 ,  H01L21/76

CPC分类号： H01L29/7813 ,  H01L21/31053 ,  H01L21/3212 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/66734

摘要： First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to planarize the exposed surfaces of the poly-1 so that the surfaces are flush with adjacent surfaces. Then, shallow trenches are formed in the substrate between the deep trenches, and second polysilicon (poly-2) is deposited into the shallow trenches. A second polysilicon polishing process is performed to planarize the exposed surface of the poly-2 so that the surface is flush with adjacent surfaces. Metal contacts to the poly-1 and the poly-2 are then formed.

摘要翻译： 第一多晶硅（poly-1）沉积在已经形成在衬底中的深沟槽中。 执行第一多晶硅抛光工艺以平坦化多晶硅-1的暴露表面，使得表面与相邻表面齐平。 然后，在深沟槽之间的衬底中形成浅沟槽，并且将第二多晶硅（poly-2）沉积到浅沟槽中。 执行第二多晶硅抛光工艺以平坦化多晶硅-2的暴露表面，使得表面与相邻表面齐平。 然后形成与poly-1和poly-2的金属接触。

公开(公告)号：US09577089B2

公开(公告)日：2017-02-21

申请号：US13039089

申请日：2011-03-02

申请人： Kyle Terrill ,  Deva Pattanayak ,  Zhiyun Luo

发明人： Kyle Terrill ,  Yuming Bai ,  Deva Pattanayak ,  Zhiyun Luo

IPC分类号： H01L21/76 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423

CPC分类号： H01L29/7813 ,  H01L21/31053 ,  H01L21/3212 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/66734

摘要： First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to planarize the exposed surfaces of the poly-1 so that the surfaces are flush with adjacent surfaces. Then, shallow trenches are formed in the substrate between the deep trenches, and second polysilicon (poly-2) is deposited into the shallow trenches. A second polysilicon polishing process is performed to planarize the exposed surface of the poly-2 so that the surface is flush with adjacent surfaces. Metal contacts to the poly-1 and the poly-2 are then formed.

摘要翻译： 第一多晶硅（poly-1）沉积在已经形成在衬底中的深沟槽中。 执行第一多晶硅抛光工艺以平坦化多晶硅-1的暴露表面，使得表面与相邻表面齐平。 然后，在深沟槽之间的衬底中形成浅沟槽，并且将第二多晶硅（poly-2）沉积到浅沟槽中。 执行第二多晶硅抛光工艺以平坦化多晶硅-2的暴露表面，使得表面与相邻表面齐平。 然后形成与poly-1和poly-2的金属接触。

公开(公告)号：US09887266B2

公开(公告)日：2018-02-06

申请号：US12069712

申请日：2008-02-11

申请人： The-Tu Chau ,  Sharon Shi ,  Qufei Chen ,  Martin Hernandez ,  Deva Pattanayak ,  Kyle Terrill ,  Kuo-In Chen

发明人： The-Tu Chau ,  Sharon Shi ,  Qufei Chen ,  Martin Hernandez ,  Deva Pattanayak ,  Kyle Terrill ,  Kuo-In Chen

IPC分类号： H01L29/08 ,  H01L29/167 ,  H01L29/78

CPC分类号： H01L29/0878 ,  H01L29/167 ,  H01L29/7813

摘要： Ultra-low drain-source resistance power MOSFET. In accordance with an embodiment of the preset invention, a semiconductor device comprises a plurality of trench power MOSFETs. The plurality of trench power MOSFETs is formed in a second epitaxial layer. The second epitaxial layer is formed adjacent and contiguous to a first epitaxial layer. The first epitaxial layer is formed adjacent and contiguous to a substrate highly doped with red Phosphorus. The novel red Phosphorus doped substrate enables a desirable low drain-source resistance.

公开(公告)号：US20120068178A1

公开(公告)日：2012-03-22

申请号：US13308375

申请日：2011-11-30

申请人： Qufei Chen ,  Robert Xu ,  Kyle Terrill ,  Deva Pattanayak

发明人： Qufei Chen ,  Robert Xu ,  Kyle Terrill ,  Deva Pattanayak

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/0814 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7808 ,  H01L29/866 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second conductivity type, forming a body region of the substrate. The method further includes forming a trench in the body region and depositing an insulating layer in the trench and over the body region wherein the insulating layer lines the trench. The method further includes filling the trench with polysilicon forming a top surface of the trench and forming a diode in the body region wherein a portion of the diode is lower than the top surface of the trench.

摘要翻译： 本发明的实施例包括制造沟槽晶体管的方法。 该方法包括形成第一导电类型的衬底并注入第二导电类型的掺杂剂，形成衬底的体区。 所述方法还包括在所述体区域中形成沟槽，并且在所述沟槽中以及在所述主体区域上沉积绝缘层，其中所述绝缘层对准所述沟槽。 该方法还包括用形成沟槽顶表面的多晶硅填充沟槽，并在体区中形成二极管，其中二极管的一部分低于沟槽的顶表面。

公开(公告)号：US20110053326A1

公开(公告)日：2011-03-03

申请号：US12549190

申请日：2009-08-27

申请人： Yang Gao ,  Kyle Terrill ,  Deva Pattanayak ,  Kuo-In Chen ,  The-Tu Chau ,  Sharon Shi ,  Qufei Chen

发明人： Yang Gao ,  Kyle Terrill ,  Deva Pattanayak ,  Kuo-In Chen ,  The-Tu Chau ,  Sharon Shi ,  Qufei Chen

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： Methods of fabricating a super junction trench power MOSFET (metal oxide semiconductor field effect transistor) device are described. A column of p-type dopant in the super junction is separated from a first column of n-type dopant by a first column of oxide and from a second column of n-type dopant by a second column of oxide. In an n-channel device, a gate element for the FET is advantageously situated over the column of p-type dopant; and in a p-channel device, a gate element for the FET is advantageously situated over the column of n-type dopant.

摘要翻译： 描述了制造超结沟槽功率MOSFET（金属氧化物半导体场效应晶体管）器件的方法。 超级结中的p型掺杂剂的列通过第一列氧化物与第一列n型掺杂剂与第二列氧化物与第二列n型掺杂剂分离。 在n沟道器件中，用于FET的栅极元件有利地位于p型掺杂剂的列上; 并且在p沟道器件中，用于FET的栅极元件有利地位于n型掺杂剂的列之上。

公开(公告)号：US09431550B2

公开(公告)日：2016-08-30

申请号：US13308375

申请日：2011-11-30

申请人： Qufei Chen ,  Robert Xu ,  Kyle Terrill ,  Deva Pattanayak

发明人： Qufei Chen ,  Robert Xu ,  Kyle Terrill ,  Deva Pattanayak

IPC分类号： H01L27/12 ,  H01L29/76 ,  H01L29/866 ,  H01L27/06 ,  H01L27/08 ,  H01L29/66 ,  H01L29/78 ,  H01L27/02

CPC分类号： H01L29/7813 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/0814 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7808 ,  H01L29/866 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second conductivity type, forming a body region of the substrate. The method further includes forming a trench in the body region and depositing an insulating layer in the trench and over the body region wherein the insulating layer lines the trench. The method further includes filling the trench with polysilicon forming a top surface of the trench and forming a diode in the body region wherein a portion of the diode is lower than the top surface of the trench.

公开(公告)号：US06709930B2

公开(公告)日：2004-03-23

申请号：US10176570

申请日：2002-06-21

申请人： Ben Chan ,  Kam Hong Lui ,  Christiana Yue ,  Ronald Wong ,  David Chang ,  Frederick P. Giles ,  Kyle Terrill ,  Mohamed N. Darwish ,  Deva Pattanayak ,  Robert Q. Xu ,  Kuo-in Chen

发明人： Ben Chan ,  Kam Hong Lui ,  Christiana Yue ,  Ronald Wong ,  David Chang ,  Frederick P. Giles ,  Kyle Terrill ,  Mohamed N. Darwish ,  Deva Pattanayak ,  Robert Q. Xu ,  Kuo-in Chen

IPC分类号： H01L21336

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/42368

摘要： A trench MOSFET is formed by creating a trench in a semiconductor substrate, then forming a barrier layer over a portion of the side wall of the trench. A thick insulating layer is deposited in the bottom of the trench. The barrier layer is selected such that the thick insulating layer deposits in the bottom of the trench at a faster rate than the thick insulating layer deposits on the barrier layer. Embodiments of the present invention avoid stress and reliability problems associated with thermal growth of insulating layers, and avoid problems with control of the shape and thickness of the thick insulating layer encountered when a thick insulating layer is deposited, then etched to the proper shape and thickness.

摘要翻译： 通过在半导体衬底中形成沟槽，然后在沟槽的侧壁的一部分上形成阻挡层来形成沟槽MOSFET。 在沟槽的底部沉积厚的绝缘层。 选择阻挡层使得厚的绝缘层以比绝缘层沉积在阻挡层上更快的速率沉积在沟槽的底部。 本发明的实施例避免了与绝缘层的热生长相关的应力和可靠性问题，并且避免了当沉积厚绝缘层时遇到的厚绝缘层的形状和厚度的控制问题，然后蚀刻到适当的形状和厚度 。

公开(公告)号：US09306056B2

公开(公告)日：2016-04-05

申请号：US12610148

申请日：2009-10-30

申请人： Deva Pattanayak ,  King Owyang ,  Mohammed Kasem ,  Kyle Terrill ,  Reuven Katraro ,  Kuo-In Chen ,  Calvin Choi ,  Qufei Chen ,  Ronald Wong ,  Kam Hong Lui ,  Robert Xu

发明人： Deva Pattanayak ,  King Owyang ,  Mohammed Kasem ,  Kyle Terrill ,  Reuven Katraro ,  Kuo-In Chen ,  Calvin Choi ,  Qufei Chen ,  Ronald Wong ,  Kam Hong Lui ,  Robert Xu

IPC分类号： H01L23/48 ,  H01L29/78 ,  H01L23/00 ,  H01L29/417 ,  H01L29/66 ,  H01L29/45

CPC分类号： H01L29/7809 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L29/408 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/456 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/06051 ,  H01L2224/13007 ,  H01L2224/13014 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.

摘要翻译： 半导体器件（例如，倒装芯片）包括通过中间层与漏极接触分离的衬底层。 通过中间层的沟槽状馈通元件用于在器件工作时电连接漏极接触和衬底层。

公开(公告)号：US08409954B2

公开(公告)日：2013-04-02

申请号：US11386927

申请日：2006-03-21

申请人： The-Tu Chau ,  Sharon Shi ,  Qufei Chen ,  Martin Hernandez ,  Deva Pattanayak ,  Kyle Terrill ,  Kuo-In Chen

发明人： The-Tu Chau ,  Sharon Shi ,  Qufei Chen ,  Martin Hernandez ,  Deva Pattanayak ,  Kyle Terrill ,  Kuo-In Chen

IPC分类号： H01L21/336

CPC分类号： H01L29/0878 ,  H01L29/167 ,  H01L29/7813

摘要： Ultra-low drain-source resistance power MOSFET. In accordance with an embodiment of the preset invention, a semiconductor device comprises a plurality of trench power MOSFETs. The plurality of trench power MOSFETs is formed in a second epitaxial layer. The second epitaxial layer is formed adjacent and contiguous to a first epitaxial layer. The first epitaxial layer is formed adjacent and contiguous to a substrate highly doped with red Phosphorous. The novel red Phosphorous doped substrate enables a desirable low drain-source resistance.

摘要翻译： 超低漏源电阻功率MOSFET。 根据本发明的实施例，半导体器件包括多个沟槽功率MOSFET。 多个沟槽功率MOSFET形成在第二外延层中。 第二外延层形成为与第一外延层相邻并邻接。 第一外延层与高度掺杂有红磷的衬底相邻并邻接地形成。 新型红磷掺杂衬底能够实现所需的低漏源电阻。

公开(公告)号：US20110101525A1

公开(公告)日：2011-05-05

申请号：US12610148

申请日：2009-10-30

申请人： Deva Pattanayak ,  King Owyang ,  Mohammed Kasem ,  Kyle Terrill ,  Reuven Katraro ,  Kuo-In Chen ,  Calvin Choi ,  Qufei Chen ,  Ronald Wong ,  Kam Hong Lui ,  Robert Xu

发明人： Deva Pattanayak ,  King Owyang ,  Mohammed Kasem ,  Kyle Terrill ,  Reuven Katraro ,  Kuo-In Chen ,  Calvin Choi ,  Qufei Chen ,  Ronald Wong ,  Kam Hong Lui ,  Robert Xu

IPC分类号： H01L23/48 ,  H01L23/488 ,  H01L21/768

CPC分类号： H01L29/7809 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L29/408 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/456 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/06051 ,  H01L2224/13007 ,  H01L2224/13014 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.

摘要翻译： 半导体器件（例如，倒装芯片）包括通过中间层与漏极接触分离的衬底层。 通过中间层的沟槽状馈通元件用于在器件工作时电连接漏极接触和衬底层。