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公开(公告)号：US20240274199A1
公开(公告)日：2024-08-15
申请号：US18166484
申请日：2023-02-09
Applicant: MACRONIX International Co., Ltd.
Inventor： Yu-Hsuan Lin , Po-Hao Tseng
CPC classification number: G11C16/08 , G11C16/0483 , G11C16/26
Abstract: A hyperdimensional computing device includes a non-volatile memory cell array and a first operation circuit. The non-volatile memory cell array is coupled to a plurality of first word lines. The non-volatile memory cell array has a plurality of memory cell groups, a plurality of first memory cells of each of the memory cell groups are coupled to a same first word line of the first word lines, and the memory cell groups respectively store a plurality of data vectors. The first operation circuit receives at least one of the data vectors through bit lines and generates a bundled data vector according to the at least one of the data vectors.
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公开(公告)号：US11804269B2
公开(公告)日：2023-10-31
申请号：US18073366
申请日：2022-12-01
Applicant: MACRONIX International Co., Ltd.
Inventor： Feng-Min Lee , Po-Hao Tseng , Yu-Hsuan Lin , Ming-Hsiu Lee
IPC: G11C16/30 , H01L29/788 , G11C16/24 , G11C16/08 , G11C16/16 , H01L29/792 , H01L29/423 , G11C11/56 , H10B41/35 , H10B41/41 , H10B43/35 , H10B43/40
CPC classification number: G11C16/30 , G11C11/5635 , G11C11/5671 , G11C16/08 , G11C16/16 , G11C16/24 , H01L29/42392 , H01L29/7885 , H01L29/792 , H10B41/35 , H10B41/41 , H10B43/35 , H10B43/40
Abstract: A flash memory cell includes a rectifying device and a transistor. The rectifying device has an input end coupled to a bit line. The transistor has a charge storage structure. The transistor has a first end coupled to an output end of the rectifying device, the transistor has a second end coupled to a source line, and a control end of the transistor is coupled to a word line.
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3.发明授权公开(公告)号：US11586418B2
公开(公告)日：2023-02-21
申请号：US16807194
申请日：2020-03-03
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Po-Hao Tseng , Ming-Hsiu Lee , Yu-Hsuan Lin
Abstract: A random number generator, a random number generating circuit, and a random number generating method are provided. The random number generating circuit includes the random number generator and executes the random number generating method. The random number generator includes a shift register having N storage elements and a combinational logic circuit. The N storage elements receive a random seed in a static state and repetitively perform a bit shift operation in a plurality of clock cycles. The combinational logic circuit generates an output sequence based on the random seed and a random bitstream received from an external source.
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公开(公告)号：US20220246218A1
公开(公告)日：2022-08-04
申请号：US17166484
申请日：2021-02-03
Applicant: MACRONIX International Co., Ltd.
Inventor： Feng-Min Lee , Po-Hao Tseng , Yu-Hsuan Lin , Ming-Hsiu Lee
IPC: G11C16/30 , H01L29/788 , G11C16/24 , G11C16/08 , G11C16/16 , H01L29/792 , H01L27/1157 , H01L27/11573 , H01L27/11524 , H01L27/11529 , G11C11/56 , H01L29/423
Abstract: A flash memory cell includes a rectifying device and a transistor. The rectifying device has an input end coupled to a bit line. The transistor has a charge storage structure. The transistor has a first end coupled to an output end of the rectifying device, the transistor has a second end coupled to a source line, and a control end of the transistor is coupled to a word line.
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公开(公告)号：US20220236951A1
公开(公告)日：2022-07-28
申请号：US17344500
申请日：2021-06-10
Applicant: MACRONIX International Co., Ltd.
Inventor： Po-Hao Tseng , Feng-Min Lee , Yu-Hsuan Lin
Abstract: A multiplication and addition operation device and a control method thereof are provided. The multiplication and addition operation device includes a feature information filter and an in-memory calculator. The feature information filter records a plurality of designated bits of a plurality of feature information, compares received input information with the designated bits to generate a comparison result, and generates a selected address according to the comparison result. The in-memory calculator records all bits of the feature information, and generates an operation result by performing a multiplication and addition operation on the feature information and the input information according to the selected address.
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Patent Agency Ranking
公开(公告)号：US10971200B2
公开(公告)日：2021-04-06
申请号：US16154831
申请日：2018-10-09
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Hsuan Lin , Chao-Hung Wang
Abstract: A semiconductor circuit and an operating method for the same are provided. The method includes the following steps. A memory circuit is operated during a first timing to obtain a first memory state signal S1. The memory circuit is operated during a second timing after the first timing to obtain a second memory state signal S2. A difference between the first memory state signal S1 and the second memory state signal S2 is calculated to obtain a state difference signal SD. A calculating is performed to obtain an un-compensated output data signal OD relative with an input data signal ID and the second memory state signal S2. The state difference signal SD and the un-compensated output data signal OD are calculated to obtain a compensated output data signal OD′.
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7.发明授权公开(公告)号：US10482953B1
公开(公告)日：2019-11-19
申请号：US16103022
申请日：2018-08-14
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Hsuan Lin , Yu-Yu Lin , Feng-Min Lee , Chao-Hung Wang , Po-Hao Tseng , Kai-Chieh Hsu
Abstract: A multi-state memory device includes a first memory element, a second memory element, a first controlling element and a second controlling element. The second memory element has a memory cell structure identical to that of the first memory element and connects to the first memory element in series. The first controlling element is connected to the first memory element either in series or in parallel. The second controlling element has a characteristic value identical to that of the first controlling element and is connected to the second memory element by a connection structure identical to that of the first controlling element. When the first memory element receives a first signal and a second signal through the first controlling element, a first state value and a second state value are generated correspondingly, and the characteristic value is greater than the first state value and less than the second state value.
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公开(公告)号：US09583536B2
公开(公告)日：2017-02-28
申请号：US14806832
申请日：2015-07-23
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Erh-Kun Lai , Chao-I Wu , Yu-Hsuan Lin , Dai-Ying Lee
CPC classification number: H01L27/2409 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/1616 , H01L45/1625 , H01L45/1633 , H01L45/1641 , H01L45/1691
Abstract: A memory device having an array area and a periphery area is provided. The memory device includes a substrate, an isolation layer formed in the substrate, a first doped region formed on the isolation layer in the array area, a second doped region formed on the first doped region, a metal silicide layer formed on the second doped region, and a metal silicide oxide layer formed on the metal silicide layer.
Abstract translation: 提供具有阵列区域和周边区域的存储器件。 存储器件包括衬底，形成在衬底中的隔离层，形成在阵列区域中的隔离层上的第一掺杂区域，形成在第一掺杂区域上的第二掺杂区域，形成在第二掺杂区域上的金属硅化物层 以及形成在金属硅化物层上的金属硅化物层。
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公开(公告)号：US20170025473A1
公开(公告)日：2017-01-26
申请号：US14806832
申请日：2015-07-23
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Erh-Kun Lai , Chao-I Wu , Yu-Hsuan Lin , Dai-Ying Lee
CPC classification number: H01L27/2409 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/1616 , H01L45/1625 , H01L45/1633 , H01L45/1641 , H01L45/1691
Abstract: A memory device having an array area and a periphery area is provided. The memory device includes a substrate, an isolation layer formed in the substrate, a first doped region formed on the isolation layer in the array area, a second doped region formed on the first doped region, a metal silicide layer formed on the second doped region, and a metal silicide oxide layer formed on the metal silicide layer.
Abstract translation: 提供具有阵列区域和周边区域的存储器件。 存储器件包括衬底，形成在衬底中的隔离层，形成在阵列区域中的隔离层上的第一掺杂区域，形成在第一掺杂区域上的第二掺杂区域，形成在第二掺杂区域上的金属硅化物层 以及形成在金属硅化物层上的金属硅化物层。
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公开(公告)号：US12182701B2
公开(公告)日：2024-12-31
申请号：US17388053
申请日：2021-07-29
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Hsuan Lin , Po-Kai Hsu , Ming-Liang Wei
IPC: G06N3/08
Abstract: The present invention discloses a memory and a training method for neural network based on memory. The training method includes: obtaining one or more transfer functions of a memory corresponding to one or more influence factors; determining a training plan according to an ideal case and the one or more influence factors; training the neural network according to the training plan and the one or more transfer functions to obtain a plurality of weights of the trained neural network; and programming the memory according to the weights.
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