公开(公告)号：US20250078932A1

公开(公告)日：2025-03-06

申请号：US18953372

申请日：2024-11-20

Applicant: Micron Technology, Inc.

Inventor： Jeffrey S. McNeil ,  Kishore Kumar Muchherla ,  Sead Zildzic ,  Akira Goda ,  Jonathan S. Parry ,  Violante Moschiano

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/28

Abstract: A system includes a memory device including a memory array and processing logic, operatively coupled with the memory array, to perform operations including identifying a set of cells of the memory array to be programmed with dummy data, and concurrently programming the set of cells with the dummy data by causing a ganged programming pulse to be applied to the set of cells.

公开(公告)号：US20250053301A1

公开(公告)日：2025-02-13

申请号：US18929570

申请日：2024-10-28

Applicant: Micron Technology, Inc,

Inventor： Jeffrey S. McNeil ,  Jonathan S. Parry ,  Ugo Russo ,  Akira Goda ,  Kishore Kumar Muchherla ,  Violante Moschiano ,  Niccolo' Righetti ,  Silvia Beltrami

IPC: G06F3/06

Abstract: Control logic in a memory device causes a first pulse to be applied to a plurality of word lines coupled to respective memory cells in a memory array. The control logic further causes a second pulse to be applied to a first set of word lines of the plurality of word lines. The control logic can cause a third pulse to be applied to a second set of word lines of the plurality of word lines and cause a fourth pulse to be applied to a source line of the memory array to erase the respective memory cells coupled to the first set of word lines and to program the respective memory cells coupled to the second set of word lines.

公开(公告)号：US20240419544A1

公开(公告)日：2024-12-19

申请号：US18821886

申请日：2024-08-30

Applicant: Micron Technology, Inc.

Inventor： Sivagnanam Parthasarathy ,  Kishore Kumar Muchherla ,  Akira Goda ,  Mustafa N. Kaynak

IPC: G06F11/10 ,  H03M13/11

Abstract: A memory device to use added known data as part of data written to memory cells with redundant data generated according to an error correction code (ECC). The code rate of the ECC may limit its capability to recover from excessive errors in the stored data. To reduce the errors, the added data retrieved from the memory cells can be corrected without using the ECC. Subsequently, remaining errors can be corrected via the ECC. Optionally, the added data can be configured to be the same as the data represented by an erased state of a subset of the memory cells such that when the subset is used to store the added data, the subset remains in the erased state to reduce wearing. Different subsets can be used to store added data for different write operations to distribute the benefit of reduced wearing.

公开(公告)号：US20240347126A1

公开(公告)日：2024-10-17

申请号：US18622190

申请日：2024-03-29

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Kishore K. Muchherla

IPC: G11C29/50

CPC classification number: G11C29/50004 ,  G11C2029/5004

Abstract: An apparatus can comprise a memory array comprising multiple erase blocks coupled to a same plurality of strings of memory cells. A controller is configured to: apply a first read pass voltage to unselected access lines of the first group of access lines in association with performing a sensing operation on a selected access line of the first group of access lines; and determine a second read pass voltage to be applied to the second group of access lines in association with performing the sensing operation on the selected access line of the first group. The second read pass voltage is determined by: determining an amount of time that the second group of memory cells has been in a programmed state; or performing a scan to determine a threshold voltage (Vt) characteristic corresponding to the second group of memory cells; or both.

公开(公告)号：US12068034B2

公开(公告)日：2024-08-20

申请号：US17899409

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Huai-Yuan Tseng ,  Giovanni Maria Paolucci ,  Dave Scott Ebsen ,  James Fitzpatrick ,  Akira Goda ,  Jeffrey S. McNeil ,  Umberto Siciliani ,  Daniel J. Hubbard ,  Walter Di Francesco ,  Michele Incarnati

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/34

CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/3404

Abstract: Exemplary methods, apparatuses, and systems including a programming manager for controlling writing data bits to a memory device. The programming manager receives a first set of data bits for programming to memory. The programming manager writes a first subset of data bits to a first wordline during a first pass of programming. The programming manager writes a second subset of data bits of the first set of data bits to a buffer. The programming manager receives a second set of data bits for programming. The programming manager writes the second subset of data bits of the first set of data bits to the first wordline during a second pass of programming to increase a bit density of memory cells in the first wordline in response to receiving the second set of data bits.

公开(公告)号：US20240231617A1

公开(公告)日：2024-07-11

申请号：US18612028

申请日：2024-03-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tomoharu Tanaka ,  Huai-Yuan Tseng ,  Dung V. Nguyen ,  Kishore Kumar Muchherla ,  Eric N. Lee ,  Akira Goda ,  James Fitzpatrick ,  Dave Ebsen

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0679

Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.

公开(公告)号：US11994947B2

公开(公告)日：2024-05-28

申请号：US17884432

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Huai-Yuan Tseng ,  Mustafa N. Kaynak ,  Akira Goda ,  Sivagnanam Parthasarathy ,  Jonathan Scott Parry

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/0793

Abstract: A system related to providing multi-layer code rates for special event protection with reduced performance penalty for memories is disclosed. Based on an impending stress event, extra error correction code data is utilized to encode user data obtained from a host. The user data and first error correction code data are written to a first block and the extra error correction code data is written to a second block. Upon stress event completion, pages having user data with the extra error correction code data are scanned. If pages of the first block are unable to satisfy reliability requirements, a touch-up process is executed on each page in the first block to reinstate the first block so that the extra error correction code data is no longer needed. The extra error correction code data is deleted from the second block and the second block is made available for user data.

公开(公告)号：US20240168879A1

公开(公告)日：2024-05-23

申请号：US18386760

申请日：2023-11-03

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Kishore K. Muchherla ,  Shyam Sunder Raghunathan ,  Leo Raimondo ,  Jung Sheng Hoei ,  Xiangang Luo ,  Ashutosh Malshe ,  Jianmin Huang

IPC: G06F12/02

CPC classification number: G06F12/0246

Abstract: An apparatus can comprise a memory array comprising a plurality of strings of memory cells each comprising: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is configured to determine a cumulative amount of read disturb stress experienced by the first erase block by monitoring read disturb stress experienced by the first erase block due to: read operations performed on the first erase block; read operations performed on the second erase block; and program verify operations performed on the second erase block. The controller can perform an action on the first erase block responsive to the cumulative amount of read disturb stress experienced by the first erase block meeting a criteria.

公开(公告)号：US11899966B2

公开(公告)日：2024-02-13

申请号：US17872206

申请日：2022-07-25

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Mark A. Helm ,  Giuseppina Puzzilli ,  Peter Feeley ,  Yifen Liu ,  Violante Moschiano ,  Akira Goda ,  Sampath K. Ratnam

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0679

Abstract: An example memory sub-system comprises: a memory device; and a processing device, operatively coupled with the memory device. The processing device is configured to: receive a first host data item; store the first host data item in a first page of a first logical unit of a memory device, wherein the first page is associated with a fault tolerant stripe; receive a second host data item; store the second host data item in a second page of the first logical unit of the memory device, wherein the second page is associated with the fault tolerant stripe, and wherein the second page is separated from the first page by one or more wordlines including a dummy wordline storing no host data; and store, in a third page of a second logical unit of the memory device, redundancy metadata associated with the fault tolerant stripe.

公开(公告)号：US20240029815A1

公开(公告)日：2024-01-25

申请号：US17872567

申请日：2022-07-25

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Akira Goda ,  Dave Scott Ebsen ,  Lakshmi Kalpana Vakati ,  Jiangli Zhu ,  Peter Feeley ,  Sanjay Subbarao ,  Vivek Shivhare ,  Fangfang Zhu

IPC: G11C29/52 ,  G11C29/02

CPC classification number: G11C29/52 ,  G11C29/022

Abstract: Methods, systems, and apparatuses include retrieving a defectivity footprint of a portion of memory, the portion of memory composed of multiple blocks. A deck programming order is determined, based on the defectivity footprint, for a current block of the multiple blocks. The current block is composed of multiple decks. The deck programming order is an order in which the multiple decks are programmed. The multiple decks programmed according to the determined deck programming order.