公开(公告)号：US10658041B1

公开(公告)日：2020-05-19

申请号：US16205755

申请日：2018-11-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luigi Pilolli ,  Agatino Massimo Maccarrone ,  Hoon Choi ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam

IPC: G11C7/10 ,  G11C16/10 ,  H03M9/00 ,  G11C16/32 ,  G11C16/04

Abstract: Methods for serializing data output including receiving a plurality of data values, sequentially providing data values representative of data values of a first subset of data values of the plurality of data values to a first signal line while sequentially providing data values representative of data values of a second subset of data values of the plurality of data values to a second signal line, and providing data values representative of the sequentially-provided data values from the first signal line and providing data values representative of the sequentially-provided data values from the second signal line in an alternating manner to a third signal line, as well as apparatus having a configuration to support such methods.

公开(公告)号：US10236052B2

公开(公告)日：2019-03-19

申请号：US15592436

申请日：2017-05-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Onegyun Na ,  Jongtae Kwak ,  Seong-Hoon Lee ,  Hoon Choi

IPC: G11C7/10 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/02 ,  G11C11/4074

Abstract: A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input of the sense amplifier. The clamping circuits may be disabled during the time that the sense amplifier is sensing the state of a memory cell at different times in a staggered manner. The clamping circuits may be effecting in making the current sense amplifier less sensitive to noise signals.

公开(公告)号：US20170285938A1

公开(公告)日：2017-10-05

申请号：US15084979

申请日：2016-03-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric Lee ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam ,  Hoon Choi ,  Daesik Song

IPC: G06F3/06 ,  G11C16/26 ,  G06F12/08 ,  G11C16/32

CPC classification number: G06F3/061 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0802 ,  G06F2212/222 ,  G06F2212/7203 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/222 ,  G11C16/26 ,  G11C16/32

Abstract: In an example, a method of operating a memory device to latch data for output from the memory device may include generating a first clock edge of a first clock signal in response to a first clock edge of a second clock signal, generating a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal, and latching the data in response to the second clock edge of the first clock signal for output from the memory device.

公开(公告)号：US20180292990A1

公开(公告)日：2018-10-11

申请号：US16006192

申请日：2018-06-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric Lee ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam ,  Hoon Choi ,  Daesik Song

IPC: G06F3/06 ,  G11C16/32 ,  G11C16/26 ,  G11C7/22 ,  G11C7/10 ,  G06F12/0802

CPC classification number: G06F3/061 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0215 ,  G06F12/0802 ,  G06F2212/1016 ,  G06F2212/2022 ,  G06F2212/222 ,  G06F2212/7203 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/222 ,  G11C16/26 ,  G11C16/32

Abstract: Memory device including a controller configured to cause the memory device to generate a first clock edge of a first clock signal in response to a first clock edge of a second clock signal, to generate a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal, and to latch data for output from the memory device in response to the second clock edge of the first clock signal.

公开(公告)号：US10019170B2

公开(公告)日：2018-07-10

申请号：US15084979

申请日：2016-03-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric Lee ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam ,  Hoon Choi ,  Daesik Song

IPC: G06F3/06 ,  G11C16/26 ,  G11C16/32 ,  G06F12/0802 ,  G11C7/10 ,  G11C7/22

CPC classification number: G06F3/061 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0215 ,  G06F12/0802 ,  G06F2212/1016 ,  G06F2212/2022 ,  G06F2212/222 ,  G06F2212/7203 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/222 ,  G11C16/26 ,  G11C16/32

Abstract: In an example, a method of operating a memory device to latch data for output from the memory device may include generating a first clock edge of a first clock signal in response to a first clock edge of a second clock signal, generating a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal, and latching the data in response to the second clock edge of the first clock signal for output from the memory device.

公开(公告)号：US20170249985A1

公开(公告)日：2017-08-31

申请号：US15592436

申请日：2017-05-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Onegyun Na ,  Jongtae Kwak ,  Seong-Hoon Lee ,  Hoon Choi

IPC: G11C11/4091 ,  G11C11/4074

CPC classification number: G11C11/4091 ,  G11C7/02 ,  G11C7/06 ,  G11C7/062 ,  G11C7/065 ,  G11C11/4074 ,  G11C2207/063 ,  G11C2207/2281

Abstract: A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input of the sense amplifier. The clamping circuits may be disabled during the time that the sense amplifier is sensing the state of a memory cell at different times in a staggered manner. The clamping circuits may be effecting in making the current sense amplifier less sensitive to noise signals.

公开(公告)号：US09479167B2

公开(公告)日：2016-10-25

申请号：US14508270

申请日：2014-10-07

Applicant: Micron Technology, Inc.

Inventor： Hoon Choi

IPC: H03K19/00 ,  G11C7/12 ,  G11C7/10 ,  G11C8/08 ,  H03K19/0175

CPC classification number: H03K19/0008 ,  G11C7/1048 ,  G11C7/12 ,  G11C8/08 ,  H03K19/0175

Abstract: Apparatuses and methods for charge sharing, between signal lines are disclosed. An example apparatus may include first and second lines and a charge sharing circuit. The charge sharing circuit may be coupled to the first line and the second line and configured to receive a first data signal and a second data signal. The charge sharing circuit may be further configured to cause charge to be shared between the first line and the second line responsive, at least in part, to the first data signal and the second data signal having different logic levels.

Abstract translation: 公开了信号线之间的电荷共享的装置和方法。 示例性装置可以包括第一和第二线路以及电荷共享电路。 电荷共享电路可以耦合到第一线路和第二线路并且被配置为接收第一数据信号和第二数据信号。 电荷共享电路还可以被配置为至少部分地响应于具有不同逻辑电平的第一数据信号和第二数据信号，使电荷在第一线路和第二线路之间共享。

公开(公告)号：US10802721B2

公开(公告)日：2020-10-13

申请号：US16398646

申请日：2019-04-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric Lee ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam ,  Hoon Choi ,  Daesik Song

IPC: G11C7/10 ,  G06F3/06 ,  G11C16/32 ,  G11C16/26 ,  G06F12/0802 ,  G11C7/22 ,  G06F12/02

Abstract: Memory device including a controller configured to cause the memory device to generate a first clock edge of a first clock signal in response to a first clock edge of a second clock signal; to generate a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal; and to latch data for output from the memory device in response to the second clock edge of the first clock signal.

公开(公告)号：US20190258400A1

公开(公告)日：2019-08-22

申请号：US16398646

申请日：2019-04-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric Lee ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam ,  Hoon Choi ,  Daesik Song

IPC: G06F3/06 ,  G11C16/26 ,  G11C16/32 ,  G11C7/10 ,  G11C7/22 ,  G06F12/0802 ,  G06F12/02

Abstract: Memory device including a controller configured to cause the memory device to generate a first clock edge of a first clock signal in response to a first clock edge of a second clock signal; to generate a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal; and to latch data for output from the memory device in response to the second clock edge of the first clock signal.

公开(公告)号：US09460803B1

公开(公告)日：2016-10-04

申请号：US14864990

申请日：2015-09-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qiang Tang ,  Ali Feiz Zarrin Ghalam ,  Hoon Choi ,  Eric N. Lee ,  Ramin Ghodsi

IPC: G11C16/26 ,  G11C7/22 ,  G11C16/32 ,  G11C7/10 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C5/063 ,  G11C7/04 ,  G11C7/08 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/222 ,  G11C16/0483 ,  G11C16/32

Abstract: A system includes a plurality of sensing devices, a first multiplexer, a plurality of local return clock signal paths, a second multiplexer, and a data latch. Each sensing device outputs data onto a respective local data path in response to a clock signal on a clock signal path. The first multiplexor passes data from a selected local data path to a global data path. Each local return clock signal path is coupled to the clock signal path at a respective sensing device such that each local return clock signal path is routed along with a respective local data path. The second multiplexor passes a return clock signal from a selected local return clock signal path corresponding to the selected local data path to a global return clock signal path. The data latch latches the data on the global data path into the data latch in response to the return clock signal on the global return clock signal path.

Abstract translation: 系统包括多个感测装置，第一多路复用器，多个本地返回时钟信号路径，第二多路复用器和数据锁存器。 每个感测装置响应于时钟信号路径上的时钟信号将数据输出到相应的本地数据路径上。 第一多路复用器将数据从选定的本地数据路径传递到全局数据路径。 每个本地返回时钟信号路径在相应感测装置处耦合到时钟信号路径，使得每个本地返回时钟信号路径与相应的本地数据路径一起路由。 第二多路复用器将来自对应于所选择的本地数据路径的选择的本地返回时钟信号路径的返回时钟信号传递到全局返回时钟信号路径。 响应于全局返回时钟信号路径上的返回时钟信号，数据锁存器将全局数据通路上的数据锁存到数据锁存器中。