公开(公告)号：US12119051B2

公开(公告)日：2024-10-15

申请号：US17884861

申请日：2022-08-10

Applicant: Micron Technology, Inc.

Inventor： Jeremy Binfet ,  Mark Helm ,  William Filipiak ,  Mark Hawes

IPC: G11C11/419 ,  G11C7/08 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C16/20 ,  G11C16/24 ,  G11C16/26 ,  G11C16/04

CPC classification number: G11C11/419 ,  G11C7/08 ,  G11C7/1015 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/227 ,  G11C16/20 ,  G11C16/24 ,  G11C16/26 ,  G11C16/0483 ,  G11C2207/2281

Abstract: Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input.

公开(公告)号：US10685702B2

公开(公告)日：2020-06-16

申请号：US15688645

申请日：2017-08-28

Applicant: Micron Technology, Inc.

Inventor： Jeremy Binfet ,  Mark Helm ,  William Filipiak ,  Mark Hawes

IPC: G11C11/419 ,  G11C16/24 ,  G11C7/10 ,  G11C7/22 ,  G11C7/08 ,  G11C16/20 ,  G11C16/26 ,  G11C7/20 ,  G11C16/04

Abstract: Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input.

公开(公告)号：US11423976B2

公开(公告)日：2022-08-23

申请号：US16896750

申请日：2020-06-09

Applicant: Micron Technology, Inc.

Inventor： Jeremy Binfet ,  Mark Helm ,  William Filipiak ,  Mark Hawes

IPC: G11C11/419 ,  G11C16/24 ,  G11C7/10 ,  G11C7/22 ,  G11C7/08 ,  G11C16/20 ,  G11C16/26 ,  G11C7/20 ,  G11C16/04

Abstract: Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input.

公开(公告)号：US10453538B2

公开(公告)日：2019-10-22

申请号：US16035933

申请日：2018-07-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Koji Sakui ,  Mark Hawes ,  Toru Tanzawa ,  Jeremy Binfet

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/14 ,  G11C16/32 ,  G11C7/04 ,  G11C16/30 ,  G11C16/34 ,  G11C16/20 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/115

Abstract: Apparatus and methods of operating such apparatus include establishing a negative potential in a body of a memory cell in response to a timer, or during an access operation of another memory cell.

公开(公告)号：US20140241097A1

公开(公告)日：2014-08-28

申请号：US13780626

申请日：2013-02-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Mark Hawes ,  Violante Moschiano

IPC: G11C8/00

CPC classification number: G11C16/20 ,  G11C29/028 ,  G11C2029/4402

Abstract: Methods of loading trim address and trim data pairs to a trim register array, and apparatus configured to perform such methods. The methods maintain a correspondence between the trim address and the trim data of each trim address and trim data pair in the trim register array. The trim address of a particular trim address and trim data pair corresponds to a storage location of a trim settings array containing trim settings used in performing operations on an array of memory cells. The trim data of the particular trim address and trim data pair corresponds to data to modify a value of the storage location of the trim settings array corresponding to the trim address of the particular trim address and trim data pair.

Abstract translation: 将修剪地址和修剪数据对加载到修剪寄存器阵列的方法以及被配置为执行这种方法的装置。 该方法保持修剪地址和修剪寄存器阵列中每个修剪地址和修剪数据对的修剪数据之间的对应关系。 特定修剪地址和修剪数据对的修剪地址对应于包含在对存储器单元阵列执行操作中使用的修剪设置的修剪设置阵列的存储位置。 特定修剪地址和修剪数据对的修剪数据对应于数据，以修改对应于特定修剪地址和修剪数据对的修剪地址的修剪设置阵列的存储位置的值。

公开(公告)号：US20220383949A1

公开(公告)日：2022-12-01

申请号：US17884861

申请日：2022-08-10

Applicant: Micron Technology, Inc.

Inventor： Jeremy Binfet ,  Mark Helm ,  William Filipiak ,  Mark Hawes

IPC: G11C11/419 ,  G11C7/08 ,  G11C7/10 ,  G11C7/20 ,  G11C16/20 ,  G11C16/24 ,  G11C16/26 ,  G11C7/22

Abstract: Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input.

公开(公告)号：US09007867B2

公开(公告)日：2015-04-14

申请号：US13780626

申请日：2013-02-28

Applicant: Micron Technology, Inc.

Inventor： Mark Hawes ,  Violante Moschiano

IPC: G11C8/00 ,  G11C16/20 ,  G11C29/02 ,  G11C29/44

CPC classification number: G11C16/20 ,  G11C29/028 ,  G11C2029/4402

Abstract: Methods of loading trim address and trim data pairs to a trim register array, and apparatus configured to perform such methods. The methods maintain a correspondence between the trim address and the trim data of each trim address and trim data pair in the trim register array. The trim address of a particular trim address and trim data pair corresponds to a storage location of a trim settings array containing trim settings used in performing operations on an array of memory cells. The trim data of the particular trim address and trim data pair corresponds to data to modify a value of the storage location of the trim settings array corresponding to the trim address of the particular trim address and trim data pair.

Abstract translation: 将修剪地址和修剪数据对加载到修剪寄存器阵列的方法以及被配置为执行这种方法的装置。 该方法保持修剪地址和修剪寄存器阵列中每个修剪地址和修剪数据对的修剪数据之间的对应关系。 特定修剪地址和修剪数据对的修剪地址对应于包含在对存储器单元阵列执行操作中使用的修剪设置的修剪设置阵列的存储位置。 特定修剪地址和修剪数据对的修剪数据对应于数据，以修改对应于特定修剪地址和修剪数据对的修剪地址的修剪设置阵列的存储位置的值。

公开(公告)号：US11710525B2

公开(公告)日：2023-07-25

申请号：US17149048

申请日：2021-01-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Koji Sakui ,  Mark Hawes ,  Toru Tanzawa ,  Jeremy Binfet

IPC: G11C11/34 ,  G11C16/26 ,  G11C7/04 ,  G11C16/30 ,  G11C16/34 ,  G11C16/20 ,  H10B41/10 ,  H10B41/27 ,  H10B41/41 ,  H10B69/00 ,  G11C16/04 ,  G11C16/08 ,  G11C16/14 ,  G11C16/32

CPC classification number: G11C16/26 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/20 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/3427 ,  H10B41/10 ,  H10B41/27 ,  H10B41/41 ,  H10B69/00

Abstract: Apparatus might include an array of memory cells and a controller to perform access operations on the array of memory cells. The controller might be configured to establish a negative potential in a body of a memory cell of the array of memory cells, and initiate a sensing operation on the memory cell while the body of the memory cell has the negative potential. Apparatus might further include an array of memory cells, a timer, and a controller to perform access operations on the array of memory cells. The controller might be configured to advance the timer, and establish a negative potential in a body of a memory cell of the array of memory cells in response to a value of the timer having a desired value.

公开(公告)号：US10916313B2

公开(公告)日：2021-02-09

申请号：US16574585

申请日：2019-09-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Koji Sakui ,  Mark Hawes ,  Toru Tanzawa ,  Jeremy Binfet

IPC: G11C16/26 ,  G11C7/04 ,  G11C16/30 ,  G11C16/34 ,  G11C16/20 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11556 ,  G11C16/04 ,  G11C16/08 ,  G11C16/14 ,  G11C16/32 ,  H01L27/115

Abstract: Apparatus configured to establish a negative potential in a body of a memory cell during an access operation of another memory cell, and methods of operating such an apparatus, as well as apparatus configured to establish a negative potential in a body of a memory cell in response to a timer, or before a sensing operation of the memory cell.

公开(公告)号：US20180322930A1

公开(公告)日：2018-11-08

申请号：US16035933

申请日：2018-07-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Koji Sakui ,  Mark Hawes ,  Toru Tanzawa ,  Jeremy Binfet

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/20 ,  G11C16/34 ,  H01L27/115 ,  G11C16/08 ,  G11C7/04 ,  G11C16/32 ,  G11C16/14 ,  G11C16/30

CPC classification number: G11C16/26 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/20 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11556

Abstract: Apparatus and methods of operating such apparatus include establishing a negative potential in a body of a memory cell in response to a timer, or during an access operation of another memory cell.