公开(公告)号：US20230005799A1

公开(公告)日：2023-01-05

申请号：US17892749

申请日：2022-08-22

Applicant: Micron Technology, Inc.

Inventor： Chiara Cerafogli ,  Kenneth William Marr ,  Brian J. Soderling ,  Michael P. Violette ,  Joshua Daniel Tomayer ,  James Eric Davis

IPC: H01L21/66 ,  H01L23/00 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11573 ,  H03K3/03 ,  H01L27/11582 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04 ,  G11C29/14 ,  H01L27/11556

Abstract: Some embodiments include apparatuses and methods of fabricating the apparatuses. One of the apparatuses includes a substrate of a semiconductor die; a memory cell portion located over a first portion of the substrate; a conductive pad portion located over a second portion of the substrate and outside the memory cell portion; and a sensor circuit including a portion located over the second portion of the substrate and under the conductive pad portion. The conductive pad portion includes conductive pads. Each of the conductive pads is part of a respective electrical path coupled to a conductive contact of a base outside the substrate.

公开(公告)号：US10276635B2

公开(公告)日：2019-04-30

申请号：US13959431

申请日：2013-08-05

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Michael P. Violette

IPC: H01L47/00 ,  H01L21/311 ,  H01L27/24 ,  H01L45/00 ,  G11C11/56 ,  H01L27/102 ,  H01L21/02 ,  H01L29/66 ,  G11C13/00

Abstract: Some embodiments include apparatus and methods having a memory device with diodes coupled to memory elements. Each diode may be formed in a recess of the memory device. The recess may have a polygonal sidewall. The diode may include a first material of a first conductivity type (e.g., n-type) and a second material of a second conductive type (e.g., p-type) formed within the recess.

公开(公告)号：US09773839B2

公开(公告)日：2017-09-26

申请号：US14790535

申请日：2015-07-02

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Michael P. Violette

IPC: H01L27/24 ,  H01L21/311 ,  H01L45/00 ,  G11C11/56 ,  H01L27/102 ,  H01L21/02 ,  H01L29/66 ,  G11C13/00

CPC classification number: H01L27/2409 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/33 ,  G11C2213/72 ,  H01L21/02532 ,  H01L21/31116 ,  H01L27/1021 ,  H01L27/2463 ,  H01L29/66136 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/144 ,  H01L45/1608

Abstract: Some embodiments include apparatus and methods having a memory device with diodes coupled to memory elements. Each diode may be formed in a recess of the memory device. The recess may have a polygonal sidewall. The diode may include a first material of a first conductivity type (e.g., n-type) and a second material of a second conductive type (e.g., p-type) formed within the recess.

公开(公告)号：US20170263865A1

公开(公告)日：2017-09-14

申请号：US15606624

申请日：2017-05-26

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Michael P. Violette

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/10 ,  H01L27/24

CPC classification number: H01L45/1608 ,  G11C13/0004 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/24 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144

Abstract: Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer spaced apart and next to the diode. Processes include the formation of one of the buried salicide word line and the metal spacer. Devices include the variable-resistance material memories and one of the buried salicided word line and the spacer word line.

公开(公告)号：US09172040B2

公开(公告)日：2015-10-27

申请号：US14463160

申请日：2014-08-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Liu ,  Michael P. Violette

IPC: H01L45/00 ,  G11C13/00 ,  H01L21/02 ,  H01L23/02 ,  H01L27/24

CPC classification number: H01L45/1608 ,  G11C13/0004 ,  H01L21/02 ,  H01L23/02 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/122 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A phase change memory cell and methods of fabricating the same are presented. The memory cell includes a variable resistance region and a top and bottom electrode. The shapes of the variable resistance region and the top electrode are configured to evenly distribute a current with a generally hemispherical current density distribution around the first electrode.

Abstract translation: 提出了相变存储单元及其制造方法。 存储单元包括可变电阻区域和顶部和底部电极。 可变电阻区域和顶部电极的形状被配置为在第一电极周围均匀地分布具有大致半球形的电流密度分布的电流。

公开(公告)号：US20150050795A1

公开(公告)日：2015-02-19

申请号：US14530935

申请日：2014-11-03

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Michael P. Violette

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1675 ,  G11C13/0014 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148

Abstract: A variable-resistance material memory (VRMM) device includes a container conductor disposed over an epitaxial semiconductive prominence that is coupled to a VRMM. A VRMM device may also include a conductive plug in a recess that is coupled to a VRMM. A VRMM array may also include a conductive plug in a surrounding recess that is coupled to a VRMM. Apparatuses include the VRMM with one of the diode constructions.

Abstract translation: 可变电阻材料存储器（VRMM）装置包括设置在耦合到VRMM的外延半导体突起上的容器导体。 VRMM装置还可以包括耦合到VRMM的凹部中的导电插头。 VRMM阵列还可以包括耦合到VRMM的周围凹部中的导电插头。 装置包括具有二极管结构之一的VRMM。

公开(公告)号：US08830738B2

公开(公告)日：2014-09-09

申请号：US13758644

申请日：2013-02-04

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Michael P. Violette

IPC: G11C11/00

CPC classification number: H01L45/143 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1675

Abstract: Some embodiments include apparatus and methods having a memory element configured to store information and an access component configured to allow conduction of current through the memory element when a first voltage difference in a first direction across the memory element and the access component exceeds a first voltage value and to prevent conduction of current through the memory element when a second voltage difference in a second direction across the memory element and the access component exceeds a second voltage value, wherein the access component includes a material excluding silicon.

Abstract translation: 一些实施例包括具有被配置为存储信息的存储器元件的设备和方法以及被配置为当存储元件和存取组件之间的第一方向上的第一电压差超过第一电压值时允许通过存储元件的电流的导通 并且当所述存储元件和所述存取组件之间的第二方向上的第二电压差超过第二电压值时，防止通过所述存储元件的电流传导，其中所述存取组件包括不包括硅的材料。

公开(公告)号：US20130313510A1

公开(公告)日：2013-11-28

申请号：US13959431

申请日：2013-08-05

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Michael P. Violette

IPC: H01L45/00

CPC classification number: H01L27/2409 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/33 ,  G11C2213/72 ,  H01L21/02532 ,  H01L21/31116 ,  H01L27/1021 ,  H01L27/2463 ,  H01L29/66136 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/144 ,  H01L45/1608

Abstract: Some embodiments include apparatus and methods having a memory device with diodes coupled to memory elements. Each diode may be formed in a recess of the memory device. The recess may have a polygonal sidewall. The diode may include a first material of a first conductivity type (e.g., n-type) and a second material of a second conductive type (e.g., p-type) formed within the recess.

公开(公告)号：US10090464B2

公开(公告)日：2018-10-02

申请号：US15606624

申请日：2017-05-26

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Michael P. Violette

IPC: H01L21/76 ,  H01L45/00 ,  G11C13/00 ,  H01L27/10 ,  H01L27/24

Abstract: Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer spaced apart and next to the diode. Processes include the formation of one of the buried salicide word line and the metal spacer. Devices include the variable-resistance material memories and one of the buried salicided word line and the spacer word line.

公开(公告)号：US10008664B2

公开(公告)日：2018-06-26

申请号：US15063238

申请日：2016-03-07

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Michael P. Violette

IPC: H01L21/00 ,  H01L45/00

CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1608 ,  H01L45/1675 ,  H01L45/1683

Abstract: Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described.