中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

40 records (took 0.014 seconds)

    3D AND flash memory device and method of fabricating the same
    1.
    发明授权
    3D AND flash memory device and method of fabricating the same 有权

    公开(公告)号：US12245428B2

    公开(公告)日：2025-03-04

    申请号：US17575418

    申请日：2022-01-13

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Hang-Ting Lue ,  Chia-Jung Chiu ,  Teng-Hao Yeh ,  Guan-Ru Lee

    IPC: H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27 ,  H01L21/786

    Abstract: A three-dimensional AND flash memory device includes a gate stack structure, a charge storage structure, a first conductive pillar and a second conductive pillar, an insulating pillar, and a channel pillar. The gate stack structure includes gate layers and insulating layers stacked alternately with each other. The first and second conductive pillars extend through the gate stack structure. The channel pillar extends through the gate stack structure. The charge storage structure is disposed between the gate stack structure and the channel pillar. The channel pillar includes: a first part and a second part connected each other. The first part is located between the charge storage structure and the insulating pillar. The second part includes a first region electrically connected to the first conductive pillar, and a second region electrically connected to the second conductive pillar. A curvature of the first part is smaller than a curvature of the second part.

    Low dielectric constant insulating material in 3D memory
    3.
    发明授权
    Low dielectric constant insulating material in 3D memory 有权

    公开(公告)号：US09721964B2

    公开(公告)日：2017-08-01

    申请号：US14297346

    申请日：2014-06-05

    Applicant: Macronix International Co., Ltd.

    Inventor： Guan-Ru Lee

    IPC: H01L27/115 ,  H01L27/11582 ,  H01L21/28

    CPC classification number: H01L27/11582 ,  H01L21/28282

    Abstract: A memory device includes a plurality of stacks of conductive strips alternating with insulating strips. At least one of the insulating strips includes an insulating material with a dielectric constant equal to or lower than 3.6. A plurality of structures of a conductive material is arranged orthogonally over the stacks. Memory elements are disposed in interface regions at cross-points between side surfaces of the stacks and structures. The insulating strips can have equivalent oxide thicknesses EOT substantially greater than their respective physical thicknesses. The EOT can be at least 10% greater than the respective physical thicknesses. The at least one of the insulating strips can consist essentially of the insulating material with a dielectric constant equal to or lower than 3.6.

    High density patterned material on integrated circuits
    4.
    发明授权
    High density patterned material on integrated circuits 有权

    公开(公告)号：US09673051B1

    公开(公告)日：2017-06-06

    申请号：US14996014

    申请日：2016-01-14

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Guan-Ru Lee

    IPC: H01L23/48 ,  H01L21/033 ,  H01L21/768 ,  H01L23/528

    CPC classification number: H01L23/5283 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76895

    Abstract: An integrated circuit comprises a plurality of strips of material over a substrate, the plurality of strips including strips S(i), each strip S(i) for i going from 3 to n having a first segment and a second segment separated by a gap from the first segment. The integrated circuit comprises a plurality of landing areas, the plurality of landing areas including landing areas A(i), each landing area A(i) for i going from 3 to n−2 connecting a first segment of strip S(i) in the plurality of strips with a second segment of strip S(i+2) in the plurality of strips, and disposed within the gap between the first and second segments in strip S(i+1). The strips S(i) have a first pitch in a direction orthogonal to the strips, and the landing areas A(i) have a second pitch twice the first pitch in the direction orthogonal to the strips of material.

    MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
    5.
    发明申请
    MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 有权
    存储器件及其制造方法

    公开(公告)号：US20160336306A1

    公开(公告)日：2016-11-17

    申请号：US14711874

    申请日：2015-05-14

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Guan-Ru Lee

    IPC: H01L27/02 ,  H01L21/306 ,  H01L29/16 ,  H01L21/283 ,  H01L27/115 ,  H01L29/04

    CPC classification number: H01L21/283 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/16

    Abstract: A memory device comprises a patterned multi-layers stacking structure, a semiconductor capping layer, a memory layer and a channel layer. The patterned multi-layers stacking structure is formed on a substrate and has at least one trench used to define a plurality of ridge-shaped stacks comprising at least one conductive strip in the patterned multi-layers stacking structure. The semiconductor capping layer covers on the ridge-shaped stacks. The memory layer covers on sidewalls of the trench. The channel layer covers on the memory layer, the semiconductor capping layer and a bottom of the trench, wherein the channel layer is directly in contact with the semiconductor capping layer.

    Abstract translation: 存储器件包括图案化的多层堆叠结构，半导体覆盖层，存储层和沟道层。 图案化的多层堆叠结构形成在基板上，并且具有至少一个沟槽，用于限定多个脊形堆叠，其包括图案化多层堆叠结构中的至少一个导电条。 半导体覆盖层覆盖在脊形堆叠上。 存储层覆盖在沟槽的侧壁上。 沟道层覆盖存储层，半导体覆盖层和沟槽的底部，其中沟道层直接与半导体覆盖层接触。

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20240373630A1

    公开(公告)日：2024-11-07

    申请号：US18312207

    申请日：2023-05-04

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Kuan-Yuan Shen ,  Guan-Ru Lee ,  Chia-Jung Chiu

    IPC: H10B43/27

    Abstract: A semiconductor device includes a staircase structure and an extension part. The stacked structure is located on a dielectric substrate. The staircase structure includes a plurality of conductive layers and a plurality of insulating layers stacked alternately on each other. The extension part is located at an end of the lower stair part of the staircase structure. The resistance value of the extension part is different from the resistance value of the plurality of conductive layers.

    3D AND FLASH MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    8.
    发明公开
    3D AND FLASH MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20230284446A1

    公开(公告)日：2023-09-07

    申请号：US17684271

    申请日：2022-03-01

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Guan-Ru Lee

    IPC: H01L27/11582

    CPC classification number: H01L27/11582

    Abstract: A 3D AND flash memory device includes a gate stack structure, a channel stack structure, a source pillar and a drain pillar, and a plurality of charge storage structures. The gate stack structure is located on the dielectric substrate. The gate stack structure includes a plurality of gate layers and a plurality of insulating layers stacked alternately with each other. The channel stack structure extends through the gate stack structure. The channel stack structure includes a plurality of channel rings spaced apart from each other. The source pillar and the drain pillar are located in the channel stack structure and are respectively electrically connected to the plurality of channel rings. The plurality of charge storage structures are located between the plurality of gate layers and the plurality of channel rings.

    3D SEMICONDUCTOR DEVICE AND ARRAY LAYOUT THEREOF
    9.
    发明公开
    3D SEMICONDUCTOR DEVICE AND ARRAY LAYOUT THEREOF 审中-公开

    公开(公告)号：US20230269944A1

    公开(公告)日：2023-08-24

    申请号：US18308594

    申请日：2023-04-27

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Hang-Ting Lue ,  Wei-Chen Chen ,  Teng-Hao Yeh ,  Guan-Ru Lee

    IPC: H10B43/27 ,  H01L23/528 ,  H10B43/10

    CPC classification number: H10B43/27 ,  H01L23/528 ,  H10B43/10 ,  H01L21/0217

    Abstract: Provided are a 3D flash memory and an array layout thereof. The 3D flash memory includes a gate stack structure, a annular channel pillar, a first source/drain pillar, a second source/drain pillar and a charge storage structure. The gate stack structure is disposed on a dielectric base and includes a plurality of gate layers electrically insulated from each other. The annular channel pillar is disposed on the dielectric base and penetrates through the gate stack structure. The first source/drain pillar and the second source/drain pillar are disposed on the dielectric base, are located within the channel pillar and penetrate through the gate stack structure. The first source/drain pillar and the second source/drain pillar are separated from each other and are each connected to the channel pillar. The charge storage structure is disposed between each of the plurality of gate layers and the channel pillar.

    Method for forming memory device
    10.
    发明授权
    Method for forming memory device 有权

    公开(公告)号：US11638379B2

    公开(公告)日：2023-04-25

    申请号：US17511829

    申请日：2021-10-27

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Min-Feng Hung ,  Chia-Jung Chiu ,  Guan-Ru Lee

    IPC: H10B43/20 ,  H01L29/417 ,  H01L21/762

    Abstract: A method for forming a memory device is provided. The memory device includes a substrate; a stack including a plurality of conductive layers and a plurality of insulating layers being alternatively stacked on the substrate; a plurality of memory structures formed on the substrate and penetrating the stack; a plurality of isolation structures formed on the substrate and penetrating the stack, wherein the isolation structures dividing the memory structures into a plurality of first memory structures and a plurality of second memory structures; and a plurality of common source pillars formed on the substrate and penetrating the stack, wherein the common source pillars directly contact the isolation structures.

Patent Agency Ranking