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    Memory device and operation method thereof
    1.
    发明授权
    Memory device and operation method thereof 有权
    存储器件及其操作方法

    公开(公告)号：US09324428B1

    公开(公告)日：2016-04-26

    申请号：US14727953

    申请日：2015-06-02

    Applicant: MACRONIX INTERNATIONAL CO., LTD. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Wei-Chih Chien ,  Yung-Han Ho

    IPC: G11C11/00 ,  G11C13/00

    CPC classification number: G11C13/0097 ,  G11C11/1675 ,  G11C11/1677 ,  G11C11/5607 ,  G11C11/5678 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0092

    Abstract: An operation method for a memory device is disclosed. An operation state of the memory device is determined. If to be operated in a first operation state, the memory device is applied by a reset pulse. If to be operated in a second operation state, the memory device is applied by the reset pulse and at least a first incremental pulse set verification current, and an allowable maximum current of the first incremental pulse set verification current is lower than a melt current. If to be operated in a third operation state, the memory device is applied by the reset pulse and at least a first identical pulse set verification current, and an allowable maximum current of the first identical pulse set verification current is lower than the melt current. If to be operated in a fourth operation state, the memory device is applied by a set pulse.

    Abstract translation: 公开了一种用于存储器件的操作方法。 确定存储器件的操作状态。 如果要在第一操作状态下操作，则通过复位脉冲施加存储器件。 如果要在第二操作状态下操作，则通过复位脉冲和至少第一增量脉冲设定验证电流施加存储器件，并且第一增量脉冲组验证电流的允许最大电流低于熔化电流。 如果要在第三操作状态下操作，则通过复位脉冲和至少第一相同的脉冲设定验证电流施加存储器件，并且第一相同脉冲设定验证电流的容许最大电流低于熔化电流。 如果要在第四操作状态下操作，则通过设定脉冲施加存储器件。

    Memory device and operation method
    2.
    发明授权
    Memory device and operation method 有权
    存储器和操作方法

    公开(公告)号：US09507663B1

    公开(公告)日：2016-11-29

    申请号：US14703183

    申请日：2015-05-04

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Hsin-Yi Ho ,  Hsiang-Lan Lung ,  Wei-Chih Chien ,  Tu-Shun Chen ,  Chia-Jung Chen

    IPC: G11C29/00 ,  G06F11/10 ,  G06F3/06

    CPC classification number: G06F3/0683 ,  G06F3/0619 ,  G06F3/064 ,  G06F11/1048

    Abstract: A memory device and an operation method thereof are provided, and the operation method of the memory device includes following steps. A programming operation is performed to write an original data into a first memory array in the memory device. The original data in the first memory array is verified, and whether to generate a write signal is determined according to a verification result. An error correction code is generated according to the original data, and the error correction code and a write address are stored temporarily in a buffer circuit of the memory device. When the write signal is generated, the error correction code and the write address in the buffer circuit are written into a second memory array in the memory device.

    Abstract translation: 提供了一种存储器件及其操作方法，并且存储器件的操作方法包括以下步骤。 执行编程操作以将原始数据写入存储器件中的第一存储器阵列。 验证第一存储器阵列中的原始数据，并根据验证结果确定是否生成写入信号。 根据原始数据生成纠错码，并将纠错码和写入地址临时存储在存储装置的缓冲电路中。 当产生写入信号时，将缓冲电路中的纠错码和写入地址写入存储器件中的第二存储器阵列。

    Low temperature transition metal oxide for memory device
    4.
    发明授权
    Low temperature transition metal oxide for memory device 有权
    用于存储器件的低温过渡金属氧化物

    公开(公告)号：US08962466B2

    公开(公告)日：2015-02-24

    申请号：US13895059

    申请日：2013-05-15

    Applicant: Macronix International Co., Ltd.

    Inventor： Feng-Min Lee ,  Erh-Kun Lai ,  Wei-Chih Chien ,  Ming-Hsiu Lee ,  Chih-Chieh Yu

    IPC: H01L29/02 ,  H01L21/3205 ,  H01L47/00 ,  H01L21/02 ,  H01L45/00

    CPC classification number: H01L21/02551 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02614 ,  H01L27/2436 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/146 ,  H01L45/1633

    Abstract: A metal oxide formed by in situ oxidation assisted by radiation induced photo-acid is described. The method includes depositing a photosensitive material over a metal surface of an electrode. Upon exposure to radiation (for example ultraviolet light), a component, such as a photo-acid generator, of the photosensitive material forms an oxidizing reactant, such as a photo acid, which causes oxidation of the metal at the metal surface. As a result of the oxidation, a layer of metal oxide is formed. The photosensitive material can then be removed, and subsequent elements of the component can be formed in contact with the metal oxide layer. The metal oxide can be a transition metal oxide by oxidation of a transition metal. The metal oxide layer can be applied as a memory element in a programmable resistance memory cell. The metal oxide can be an element of a programmable metallization cell.

    Abstract translation: 描述了通过由辐射诱导的光酸辅助的原位氧化形成的金属氧化物。 该方法包括将感光材料沉积在电极的金属表面上。 感光材料暴露于辐射（例如紫外光）时，诸如光酸产生剂的组分形成氧化反应物，例如导致金属在金属表面氧化的光酸。 作为氧化的结果，形成金属氧化物层。 然后可以去除感光材料，并且可以将元件的后续元件形成为与金属氧化物层接触。 金属氧化物可以通过过渡金属的氧化而成为过渡金属氧化物。 金属氧化物层可以作为可编程电阻存储单元中的存储元件来应用。 金属氧化物可以是可编程金属化电池的元件。

    Graded metal oxide resistance based semiconductor memory device
    6.
    发明授权
    Graded metal oxide resistance based semiconductor memory device 有权
    基于分级金属氧化物电阻的半导体存储器件

    公开(公告)号：US08772106B2

    公开(公告)日：2014-07-08

    申请号：US13937465

    申请日：2013-07-09

    Applicant: Macronix International Co., Ltd.

    Inventor： Ming-Daou Lee ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh ,  Wei-Chih Chien ,  Chien Hung Yeh

    IPC: H01L21/00 ,  H01L21/16 ,  H01L21/8234 ,  H01L21/8244 ,  H01L21/8222

    CPC classification number: H01L45/1608 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/112

    Abstract: Memory devices are described along with methods for manufacturing and methods for operating. A memory device as described herein includes a plurality of memory cells located between word lines and bit lines. Memory cells in the plurality of memory cells comprise a diode and a metal-oxide memory element programmable to a plurality of resistance states including a first and a second resistance state, the diode of the memory element arranged in electrical series along a current path between a corresponding word line and a corresponding bit line. The device further includes bias circuitry to apply bias arrangements across the series arrangement of the diode and the memory element of a selected memory cell in the plurality of memory cells.

    Abstract translation: 描述存储器件以及用于制造的方法和操作方法。 如本文所述的存储器件包括位于字线和位线之间的多个存储器单元。 多个存储单元中的存储单元包括可编程为包括第一和第二电阻状态的多个电阻状态的二极管和金属氧化物存储元件，存储元件的二极管沿着电流串联布置在 对应的字线和相应的位线。 该装置还包括偏置电路，以跨越二极管的串联装置和多个存储单元中所选存储单元的存储元件施加偏置装置。

    GRADED METAL OXIDE RESISTANCE BASED SEMICONDUCTOR MEMORY DEVICE
    7.
    发明申请
    GRADED METAL OXIDE RESISTANCE BASED SEMICONDUCTOR MEMORY DEVICE 有权
    基于金属氧化物电阻的半导体存储器件

    公开(公告)号：US20130295719A1

    公开(公告)日：2013-11-07

    申请号：US13937465

    申请日：2013-07-09

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Ming-Daou Lee ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh ,  Wei-Chih Chien ,  Chien Hung Yeh

    IPC: H01L45/00

    CPC classification number: H01L45/1608 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/112

    Abstract: Memory devices are described along with methods for manufacturing and methods for operating. A memory device as described herein includes a plurality of memory cells located between word lines and bit lines. Memory cells in the plurality of memory cells comprise a diode and a metal-oxide memory element programmable to a plurality of resistance states including a first and a second resistance state, the diode of the memory element arranged in electrical series along a current path between a corresponding word line and a corresponding bit line. The device further includes bias circuitry to apply bias arrangements across the series arrangement of the diode and the memory element of a selected memory cell in the plurality of memory cells.

    Abstract translation: 描述存储器件以及用于制造的方法和操作方法。 如本文所述的存储器件包括位于字线和位线之间的多个存储器单元。 多个存储单元中的存储单元包括可编程为包括第一和第二电阻状态的多个电阻状态的二极管和金属氧化物存储元件，存储元件的二极管沿着电流串联布置在 对应的字线和相应的位线。 该装置还包括偏置电路，以跨越二极管的串联装置和多个存储单元中所选存储单元的存储元件施加偏置装置。

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