公开(公告)号：US20190279726A1

公开(公告)日：2019-09-12

申请号：US15917037

申请日：2018-03-09

Applicant: Macronix International Co., Ltd.

Inventor： Chia-Ching Li ,  Yi-Ching Liu

IPC: G11C16/28 ,  G11C16/04 ,  G11C11/408 ,  G11C11/4099 ,  G06F12/02

Abstract: A memory device comprising: a memory cell array and a memory controller configured to program data to memory cells during a programming cycle using operations comprising: during a setup stage, providing a first voltage level to word lines, a second voltage level to a first dummy word line, and a fourth voltage level to second dummy word lines being different from the first dummy word line, wherein the first voltage level is lower than a threshold voltage of a first transistor coupled to the first dummy word line and the second voltage level and the fourth voltage are higher than the threshold voltage, during a program stage, providing a third voltage level to first word lines to program data to memory cells coupled to the first word lines, the second voltage level to the first dummy word line, and the fourth voltage level to the second dummy word lines.

公开(公告)号：US10304540B1

公开(公告)日：2019-05-28

申请号：US15841688

申请日：2017-12-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-He Chiang ,  Yi-Ching Liu

IPC: G11C16/04 ,  G11C16/12 ,  G11C11/4074 ,  G11C11/4096 ,  G11C7/06 ,  G06F13/40 ,  G11C7/12

CPC classification number: G11C16/12 ,  G06F13/4004 ,  G11C7/06 ,  G11C7/12 ,  G11C11/4074 ,  G11C11/4096 ,  G11C16/0483

Abstract: A memory device includes a memory array including a number of memory cell strings, a number of bit lines, a number of pre-charge circuits coupled to the memory cell strings, and a number of sense amplifier circuits coupled to the memory cell strings through the bit lines. Each memory cell string includes at least one first select transistor, a second select transistor and at least one memory cell. Each bit line includes a third select transistor, and is coupled to a memory cell string. During a pre-charging stage, the pre-charge circuits provide a first voltage to pre-charge the memory cell strings. During a programming stage, for the memory cell strings to be inhibited, the sense amplifier circuits provide a second voltage lower than the first voltage. For the memory cell strings to be programmed, the sense amplifier circuits provide a third voltage lower than the second voltage.

公开(公告)号：US20150333736A1

公开(公告)日：2015-11-19

申请号：US14279004

申请日：2014-05-15

Applicant: MACRONIX International Co., Ltd.

Inventor： Hsien-Hung Wu ,  Yi-Ching Liu ,  Shin-Jang Shen

IPC: H03K3/011

CPC classification number: H03K3/011 ,  H03B5/1265 ,  H03K3/0231 ,  H03K4/48

Abstract: A method and a circuit for generating a clock signal from a clock integrated circuit are introduced herein. A compensation voltage is generated according to a temperature coefficient of a resistor and a clock period of a clock circuit, where the compensation voltage is resistor-corner independent. The clock period of the clock circuit is determined by the resistor and at least one capacitor of the clock circuit. The temperature dependence of the clock period of the clock circuit is reduced according to the compensation voltage.

Abstract translation: 这里介绍了用于从时钟集成电路产生时钟信号的方法和电路。 根据电阻的温度系数和时钟电路的时钟周期产生补偿电压，其中补偿电压为电阻 - 角独立。 时钟电路的时钟周期由电阻器和时钟电路的至少一个电容器确定。 根据补偿电压，时钟电路的时钟周期的温度依赖性降低。

公开(公告)号：US09391597B2

公开(公告)日：2016-07-12

申请号：US14077945

申请日：2013-11-12

Applicant: Macronix International Co., Ltd.

Inventor： Chih-Ting Hu ,  Shin-Jang Shen ,  Yi-Ching Liu

IPC: G05F1/10 ,  H03K5/003 ,  H03K3/356 ,  H02M3/07

CPC classification number: H02M3/07 ,  H03K3/356104 ,  H03K5/003 ,  H03K5/05

Abstract: A boost circuit includes a power rail to provide a supply voltage, a switch transistor controlling output of a boosted signal from a source of the switch transistor, and a timing and voltage control circuit configured to generate an equalization (EQ) signal to be applied to a gate of the switch transistor. The EQ waveform has a level being an EQ high level, an EQ low level lower than the EQ high level, or an EQ clamped level between the EQ low level and the EQ high level.

Abstract translation: 升压电路包括提供电源电压的电源轨，控制来自开关晶体管的源极的升压信号的输出的开关晶体管，以及定时和电压控制电路，其被配置为产生要应用于 开关晶体管的栅极。 EQ波形的电平为EQ高电平，EQ低电平低于EQ高电平，或EQ钳位电平在EQ低电平和EQ高电平之间。

公开(公告)号：US20150131344A1

公开(公告)日：2015-05-14

申请号：US14077945

申请日：2013-11-12

Applicant: Macronix International Co., Ltd.

Inventor： Chih-Ting Hu ,  Shin-Jang Shen ,  Yi-Ching Liu

IPC: H02M3/155

CPC classification number: H02M3/07 ,  H03K3/356104 ,  H03K5/003 ,  H03K5/05

Abstract: A boost circuit includes a power rail to provide a supply voltage, a switch transistor controlling output of a boosted signal from a source of the switch transistor, and a timing and voltage control circuit configured to generate an equalization (EQ) signal to be applied to a gate of the switch transistor. The EQ waveform has a level being an EQ high level, an EQ low level lower than the EQ high level, or an EQ clamped level between the EQ low level and the EQ high level.

Abstract translation: 升压电路包括提供电源电压的电源轨，控制来自开关晶体管的源极的升压信号的输出的开关晶体管，以及定时和电压控制电路，其被配置为产生要应用于 开关晶体管的栅极。 EQ波形的电平为EQ高电平，EQ低电平低于EQ高电平，或EQ钳位电平在EQ低电平和EQ高电平之间。

公开(公告)号：US11934480B2

公开(公告)日：2024-03-19

申请号：US16508189

申请日：2019-07-10

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue ,  Hung-Sheng Chang ,  Yi-Ching Liu

IPC: G06F17/00 ,  G06F17/16 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

CPC classification number: G06F17/16 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

Abstract: A circuit for in-memory multiply-and-accumulate functions includes a plurality of NAND blocks. A NAND block includes an array of NAND strings, including B columns and S rows, and L levels of memory cells. W word lines are coupled to (B*S) memory cells in respective levels in the L levels. A source line is coupled to the (B*S) NAND strings in the block. String select line drivers supply voltages to connect NAND strings on multiple string select lines to corresponding bit lines simultaneously. Word line drivers are coupled to apply word line voltages to a word line or word lines in a selected level. A plurality of bit line drivers apply input data to the B bit lines simultaneously. A current sensing circuit is coupled to the source line.

公开(公告)号：US10607661B1

公开(公告)日：2020-03-31

申请号：US16274299

申请日：2019-02-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao Yeh ,  Yi-Ching Liu

IPC: G11C7/00 ,  G11C5/14 ,  G11C5/02 ,  G11C5/06 ,  G11C16/04 ,  G11C11/408 ,  G11C7/18 ,  G11C8/08 ,  G11C11/4074

Abstract: A memory device and a control method thereof are provided. The memory device includes I memory blocks, I global power lines and I first local driver modules. Each memory block includes M gate control lines and a plurality of transistor units arranged in M rows. Gates of the transistor units in the m-th row are electrically connected to the m-th gate control line. The I global power lines are electrically connected to I pre-driver circuits and the I memory blocks, respectively. Each first local driver module is electrically connected to one global power line and one memory block. Each first local driver module includes M first local driver circuits. The m-th first local driver circuit is electrically connected to the m-th gate control line.

公开(公告)号：US20140258811A1

公开(公告)日：2014-09-11

申请号：US13951130

申请日：2013-07-25

Applicant: Macronix International Co., Ltd.

Inventor： Yi-Ching Liu ,  Chi Lo ,  Shuo-Nan Hung ,  Chun-Hsiung Hung

IPC: G06F11/10 ,  G06F12/00

CPC classification number: G06F11/1044 ,  G06F11/1008 ,  G06F11/1068 ,  G11B20/1833 ,  G11C7/1006

Abstract: A device includes a memory array storing data and error correcting codes ECCs corresponding to the data, and a multi-level buffer structure between the memory array and an input/output data path. The memory array includes a plurality of data lines for page mode operations. The buffer structure includes a first buffer having storage cells connected to respective data lines in the plurality of data lines for a page of data, a second buffer coupled to the storage cells in the first buffer for storing at least one page of data, and a third buffer coupled to the second buffer and to the input/output data path. The device includes logic coupled to the multi-level buffer to perform a logical process over pages of data during movement between the memory array and the input/output path through the multi-level buffer for at least one of page read and page write operations.

Abstract translation: 一种设备包括存储与数据相对应的数据和纠错码ECC的存储器阵列，以及存储器阵列和输入/输出数据路径之间的多级缓冲器结构。 存储器阵列包括用于页模式操作的多条数据线。 缓冲器结构包括：第一缓冲器，其具有连接到用于数据页的多条数据线中的相应数据线的存储单元;耦合到第一缓冲器中用于存储至少一页数据的存储单元的第二缓冲器;以及 耦合到第二缓冲器和输入/输出数据路径的第三缓冲器。 该设备包括耦合到多级缓冲器的逻辑，用于在存储器阵列和通过多级缓冲器的输入/输出路径之间的移动期间在页面读取和页面写入操作中的至少一个上执行数据页面上的逻辑处理。

公开(公告)号：US11189339B1

公开(公告)日：2021-11-30

申请号：US16886995

申请日：2020-05-29

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yi-Ching Liu ,  Chi Lo

IPC: G11C16/10 ,  G11C11/4096 ,  G11C11/4091 ,  G11C11/4094 ,  G05F3/26 ,  G11C11/4074 ,  H03M1/46 ,  G06F9/38 ,  G11C11/408 ,  G11C13/00 ,  G11C16/04

Abstract: A memory device includes: a memory array including a plurality of memory cells and a plurality of bit lines; and a current converting circuit, coupled to the memory array. In executing a calculation operation, the memory cells of the memory array generate a source current corresponding to a calculation operation result. The source current is converted by the current converting circuit into an output value for being an input signal provided to a next calculation operation.

公开(公告)号：US11056195B1

公开(公告)日：2021-07-06

申请号：US16858813

申请日：2020-04-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yi-Ching Liu ,  Chin-Ming Yang

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/24 ,  G11C29/44 ,  G11C16/26 ,  G11C16/10 ,  G11C16/14

Abstract: A driving method of a nonvolatile memory device including multiple memory planes includes following operations: precharging at least one word line and at least one bit line of a first memory plane; if the at least one word line and the at least one bit line of the first memory plane have been precharged for a first time length or to respective voltage thresholds, precharging at least one word line and at least one bit line of a second memory plane; conducting a first data operation to at least one memory cell of the first memory plane disposed at intersections of the at least one word line and the at least one bit line thereof; conducting a second data operation to at least one memory cell of the second memory plane disposed at intersections of the at least one word line and the at least one bit line thereof.