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    Semiconductor memory device and manufacturing method thereof
    3.
    发明授权
    Semiconductor memory device and manufacturing method thereof 有权
    半导体存储器件及其制造方法

    公开(公告)号：US08659070B2

    公开(公告)日：2014-02-25

    申请号：US12561451

    申请日：2009-09-17

    申请人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kido ,  Masaru Kito ,  Mitsuru Sato

    发明人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kido ,  Masaru Kito ,  Mitsuru Sato

    IPC分类号： H01L29/792

    CPC分类号： H01L29/792 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7881 ,  H01L29/7926

    摘要： The semiconductor memory device of the present invention includes a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, the memory strings having a column shaped semiconductor, a first insulation film formed around the column shaped semiconductor, a charge accumulation layer formed around the first insulation film, a second insulation film formed around the charge accumulation film and a plurality of electrodes formed around the second insulation film, a bit line connected to one end of the memory strings via a plurality of selection transistors, and a conducting layer extending in two dimensions and in which the plurality of electrodes of the memory strings and the plurality of electrodes of different memory strings are shared respectively, wherein each end part of the conducting layer is formed in step shapes in a direction parallel with the bit line.

    摘要翻译： 本发明的半导体存储器件包括具有串联连接的多个电可再编程存储器单元的多个存储器串，具有列形半导体的存储器串，形成在柱状半导体周围的第一绝缘膜，电荷累积层 形成在第一绝缘膜周围，形成在电荷累积膜周围的第二绝缘膜和围绕第二绝缘膜形成的多个电极，经由多个选择晶体管连接到存储器串的一端的位线，以及导电 分别在存储器串的多个电极和不同的存储器串的多个电极中分别共享，其中导电层的每个端部在平行于位线的方向上形成为台阶形状 。

    Non-volatile semiconductor storage device and method of manufacturing the same
    4.
    发明授权
    Non-volatile semiconductor storage device and method of manufacturing the same 有权
    非易失性半导体存储装置及其制造方法

    公开(公告)号：US08253187B2

    公开(公告)日：2012-08-28

    申请号：US12142289

    申请日：2008-06-19

    申请人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kido ,  Hideaki Aochi ,  Mitsuru Sato ,  Yasuyuki Matsuoka

    发明人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kido ,  Hideaki Aochi ,  Mitsuru Sato ,  Yasuyuki Matsuoka

    IPC分类号： H01L27/115

    CPC分类号： H01L27/115 ,  H01L27/11556

    摘要： A non-volatile semiconductor storage device 10 has a plurality of memory strings 100 with a plurality of electrically rewritable memory transistors MTr1-MTr4 connected in series. The memory string 100 includes a columnar semiconductor CLmn extending in a direction perpendicular to a substrate, a plurality of charge accumulation layers formed around the columnar semiconductor CLmn via insulating films, and selection gate lines on the drain side SGD contacting the columnar semiconductor to configure transistors. The selection gate lines on the drain side SGD have lower selection gate lines on the drain side SGDd, each of which is arranged with an interval with a certain pitch, and upper selection gate lines on the drain side SGDu located on a higher layer than the lower selection gate lines on the drain side SGDd, each of which is arranged on gaps between the lower selection gate lines on the drain side SGDd.

    摘要翻译： 非易失性半导体存储装置10具有多个串联连接的多个电可重写存储晶体管MTr1-MTr4的存储器串100。 存储器串100包括沿垂直于衬底的方向延伸的柱状半导体CLmn，经由绝缘膜形成在柱状半导体CLmn周围的多个电荷累积层，以及与柱状半导体接触的漏极侧SGD上的选择栅极线，以配置晶体管 。 漏极侧SGD上的选择栅极线在漏极侧SGDd上具有较低的选择栅极线，每个栅极配置有一定间距的间隔，漏极侧SGDu上的选择栅极线位于高于 漏极侧SGDd上的下部选择栅极线设置在漏极侧SGDd的下部选择栅极线之间的间隙。

    NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
    5.
    发明申请
    NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    非挥发性半导体存储器件及其制造方法

    公开(公告)号：US20080315296A1

    公开(公告)日：2008-12-25

    申请号：US12142289

    申请日：2008-06-19

    申请人： Hiroyasu TANAKA ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kido ,  Hideaki Aochi ,  Mitsuru Sato ,  Yasuyuki Matsuoka

    发明人： Hiroyasu TANAKA ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kido ,  Hideaki Aochi ,  Mitsuru Sato ,  Yasuyuki Matsuoka

    IPC分类号： H01L27/115 ,  H01L21/8247

    CPC分类号： H01L27/115 ,  H01L27/11556

    摘要： A non-volatile semiconductor storage device 10 has a plurality of memory strings 100 with a plurality of electrically rewritable memory transistors MTr1-MTr4 connected in series. The memory string 100 includes a columnar semiconductor CLmn extending in a direction perpendicular to a substrate, a plurality of charge accumulation layers formed around the columnar semiconductor CLmn via insulating films, and selection gate lines on the drain side SGD contacting the columnar semiconductor to configure transistors. The selection gate lines on the drain side SGD have lower selection gate lines on the drain side SGDd, each of which is arranged with an interval with a certain pitch, and upper selection gate lines on the drain side SGDu located on a higher layer than the lower selection gate lines on the drain side SGDd, each of which is arranged on gaps between the lower selection gate lines on the drain side SGDd.

    摘要翻译： 非易失性半导体存储装置10具有多个串联连接的多个电可重写存储晶体管MTr1-MTr4的存储器串100。 存储器串100包括沿垂直于衬底的方向延伸的柱状半导体CLmn，经由绝缘膜形成在柱状半导体CLmn周围的多个电荷累积层，以及与柱状半导体接触的漏极侧SGD上的选择栅极线，以配置晶体管 。 漏极侧SGD上的选择栅极线在漏极侧SGDd上具有较低的选择栅极线，每个栅极配置有一定间距的间隔，漏极侧SGDu上的选择栅极线位于高于 漏极侧SGDd上的下部选择栅极线设置在漏极侧SGDd的下部选择栅极线之间的间隙。

    Semiconductor device having trench capacitor and fabrication method for the same
    6.
    发明申请
    Semiconductor device having trench capacitor and fabrication method for the same 审中-公开
    具有沟槽电容器的半导体器件及其制造方法

    公开(公告)号：US20050145914A1

    公开(公告)日：2005-07-07

    申请号：US10892496

    申请日：2004-07-16

    申请人： Toshiharu Tanaka ,  Hideaki Aochi ,  Masaru Kito ,  Masaru Kido

    发明人： Toshiharu Tanaka ,  Hideaki Aochi ,  Masaru Kito ,  Masaru Kido

    IPC分类号： H01L27/108 ,  H01L21/334 ,  H01L21/8242 ,  H01L29/94 ,  H01L21/20 ,  H01L29/76

    CPC分类号： H01L27/10867 ,  H01L29/66181 ,  H01L29/945

    摘要： A semiconductor memory includes a semiconductor substrate; a capacitor arranged in a lower portion of the trench; a collar oxide film arranged on a side of the trench above the capacitor and having an upper collar member and a lower collar member, the upper collar member being thinner than the lower collar member so as to provide a height difference therebetween; a storage node arranged on a side of the collar oxide film; a select transistor provided on the semiconductor substrate and having a doped layer in contact with the collar oxide film; and a conductor portion arranged upon the storage node and the doped layer.

    摘要翻译： 半导体存储器包括半导体衬底; 布置在沟槽的下部的电容器; 环形氧化膜，布置在电容器上方的沟槽的一侧，并具有上衣领构件和下衣领构件，上衣领构件比下衣领构件更薄，以便在它们之间提供高度差; 布置在所述轴环氧化膜侧的存储节点; 设置在半导体衬底上并具有与环氧化膜接触的掺杂层的选择晶体管; 以及布置在存储节点和掺杂层上的导体部分。

    Nonvolatile semiconductor memory device
    7.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US08653577B2

    公开(公告)日：2014-02-18

    申请号：US13003644

    申请日：2009-07-01

    申请人： Yoshiaki Fukuzumi ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh

    发明人： Yoshiaki Fukuzumi ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh

    IPC分类号： H01L29/788 ,  H01L29/792

    CPC分类号： H01L29/7926 ,  G11C16/0466 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582

    摘要： A nonvolatile semiconductor memory device includes: a stacked body in which insulating films and electrode films are alternately stacked; selection gate electrodes provided on the stacked body; bit lines provided on the selection gate electrodes; semiconductor pillars; connective members separated from one another; and a charge storage layer provided between the electrode film and the semiconductor pillar. One of the connective members is connected between a lower part of one of the semiconductor pillars and a lower part of another of the semiconductor pillars. The one of the semiconductor pillars passes through one of the selection gate electrodes and is connected to one of the bit lines, and the another of the semiconductor pillars passes through another of the selection gate electrodes and is connected to another of the bit lines.

    摘要翻译： 非易失性半导体存储器件包括：绝缘膜和电极膜交替层叠的层叠体; 设置在层叠体上的选择栅电极; 设置在选择栅电极上的位线; 半导体柱 连接成员彼此分离; 以及设置在电极膜和半导体柱之间的电荷存储层。 一个连接构件连接在一个半导体柱的下部和另一个半导体柱的下部之间。 半导体柱中的一个穿过选择栅极之一并连接到一个位线，并且另一个半导体柱通过另一个选择栅电极并连接到另一个位线。

    Nonvolatile semiconductor memory device
    8.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US08350326B2

    公开(公告)日：2013-01-08

    申请号：US12839895

    申请日：2010-07-20

    申请人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Hideaki Aochi

    发明人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Hideaki Aochi

    IPC分类号： H01L29/792

    CPC分类号： H01L29/7926 ,  H01L21/28282 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/42344 ,  H01L29/66833

    摘要： According to one embodiment, a nonvolatile semiconductor memory device includes first and second stacked structural bodies, first and second semiconductor pillars, a memory unit connection portion, a selection unit stacked structural body, first and second selection unit semiconductor pillars, a selection unit connection portion, and first to fifth interconnections. The semiconductor pillars pierce the stacked structural bodies. The first and second interconnections are connected to the first and second semiconductor pillars, respectively. The memory unit connection portion connects the first and second semiconductor pillars. The selection unit semiconductor pillars pierce the selection unit stacked structural body. The third and fourth interconnections are connected to the first and second selection unit semiconductor pillars, respectively. The selection unit connection portion connects the first and second selection unit semiconductor pillars. The fifth interconnection is connected to the third interconnection on a side opposite to the selection unit stacked structural body.

    摘要翻译： 根据一个实施例，非易失性半导体存储器件包括第一和第二堆叠结构体，第一和第二半导体柱，存储单元连接部分，选择单元堆叠结构体，第一和第二选择单元半导体柱，选择单元连接部分 ，以及第一至第五互连。 半导体支柱刺穿堆叠的结构体。 第一和第二互连分别连接到第一和第二半导体柱。 存储单元连接部连接第一和第二半导体柱。 选择单元半导体柱刺穿选择单元堆叠结构体。 第三和第四互连分别连接到第一和第二选择单元半导体柱。 选择单元连接部分连接第一和第二选择单元半导体柱。 第五互连在与选择单元堆叠结构体相反的一侧连接到第三互连。

    Semiconductor memory device and method for manufacturing same
    9.
    发明授权
    Semiconductor memory device and method for manufacturing same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US08338882B2

    公开(公告)日：2012-12-25

    申请号：US12841662

    申请日：2010-07-22

    申请人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

    发明人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11578 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

    摘要： According to one embodiment, a semiconductor memory device includes a base, a stacked body, a memory film, a channel body, an interconnection, and a contact plug. The base includes a substrate and a peripheral circuit formed on a surface of the substrate. The stacked body includes a plurality of conductive layers and a plurality of insulating layers alternately stacked above the base. The memory film is provided on an inner wall of a memory hole punched through the stacked body to reach a lowermost layer of the conductive layers. The memory film includes a charge storage film. The interconnection is provided below the stacked body. The interconnection electrically connects the lowermost layer of the conductive layers in an interconnection region laid out on an outside of a memory cell array region and the peripheral circuit. The contact plug pierces the stacked body in the interconnection region to reach the lowermost layer of the conductive layers in the interconnection region.

    摘要翻译： 根据一个实施例，半导体存储器件包括基底，堆叠体，存储膜，通道体，互连和接触插塞。 基底包括形成在基片的表面上的基片和外围电路。 堆叠体包括多个导电层和交替堆叠在基底之上的多个绝缘层。 记忆膜设置在通过层叠体冲压的存储孔的内壁上，以到达导电层的最下层。 记忆膜包括电荷存储膜。 互连设置在堆叠体的下方。 互连电连接布置在存储单元阵列区域的外部的互连区域中的导电层的最下层和外围电路。 接触插塞刺穿互连区域中的层叠体到达互连区域中的导电层的最下层。

    Multi-layer memory device including vertical and U-shape charge storage regions
    10.
    发明授权
    Multi-layer memory device including vertical and U-shape charge storage regions 失效
    多层存储器件包括垂直和U形电荷存储区域

    公开(公告)号：US08294191B2

    公开(公告)日：2012-10-23

    申请号：US12943349

    申请日：2010-11-10

    申请人： Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Masaru Kidoh ,  Ryouhei Kirisawa

    发明人： Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Masaru Kidoh ,  Ryouhei Kirisawa

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/11573

    摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a first and a second stacked structure, a first and a second semiconductor pillar, a semiconductor connection portion, a first and a second connection portion conductive layer, a first and a second pillar portion memory layer, a first and a second connection portion memory layer. The first and second stacked structures include electrode films and inter-electrode insulating films alternately stacked in a first direction. The second stacked structure is adjacent to the first stacked structure. The first and second semiconductor pillars pierce the first and second stacked structures, respectively. The semiconductor connection portion connects the first and second semiconductor pillars. The first and second pillar portion memory layers are provided between the electrode films and the semiconductor pillar. The first and second connection portion memory layers are provided between the connection portion conductive layers and the semiconductor connection portion.

    摘要翻译： 根据一个实施例，非易失性半导体存储器件包括第一和第二堆叠结构，第一和第二半导体柱，半导体连接部分，第一和第二连接部分导电层，第一和第二柱部存储器 层，第一和第二连接部分存储层。 第一和第二堆叠结构包括在第一方向上交替堆叠的电极膜和电极间绝缘膜。 第二堆叠结构与第一堆叠结构相邻。 第一和第二半导体柱分别刺穿第一和第二堆叠结构。 半导体连接部分连接第一和第二半导体柱。 第一和第二柱部存储层设置在电极膜和半导体柱之间。 第一和第二连接部分存储层设置在连接部分导电层和半导体连接部分之间。