公开(公告)号：US09472461B2

公开(公告)日：2016-10-18

申请号：US14567445

申请日：2014-12-11

Applicant: Micron Technology, Inc.

Inventor： Werner Juengling ,  Howard C. Kirsch

IPC: H01L21/20 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/108 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L21/762 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10891 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/66484 ,  H01L29/66787 ,  H01L29/7855

Abstract: A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein the first gate is formed above the second gate. The device includes a third gate and a fourth gate formed on a second sidewall of the fin in a second trench, wherein the third gate is formed above the fourth gate. Methods of manufacturing and operating the device are also included. A method of operation may include biasing the first gate and the fourth gate to create a current path across the fin.

公开(公告)号：US20150093869A1

公开(公告)日：2015-04-02

申请号：US14567445

申请日：2014-12-11

Applicant: Micron Technology, Inc.

Inventor： Werner Juengling ,  Howard C. Kirsch

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/762 ,  H01L29/08

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10891 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/66484 ,  H01L29/66787 ,  H01L29/7855

Abstract: A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein the first gate is formed above the second gate. The device includes a third gate and a fourth gate formed on a second sidewall of the fin in a second trench, wherein the third gate is formed above the fourth gate. Methods of manufacturing and operating the device are also included. A method of operation may include biasing the first gate and the fourth gate to create a current path across the fin.

Abstract translation: 提供一种半导体器件，其包括在第一沟槽中形成有鳍状物的第一侧壁上的第一栅极和第二栅极的鳍片，其中第一栅极形成在第二栅极之上。 该器件包括在第二沟槽中形成在鳍片的第二侧壁上的第三栅极和第四栅极，其中第三栅极形成在第四栅极之上。 还包括制造和操作设备的方法。 一种操作方法可以包括偏置第一栅极和第四栅极以产生穿过散热片的电流路径。

公开(公告)号：US09190126B2

公开(公告)日：2015-11-17

申请号：US14094466

申请日：2013-12-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： J. Wayne Thompson ,  Howard C. Kirsch ,  Charles L. Ingalls

IPC: G01R19/00 ,  G11C7/12 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/4094

CPC classification number: G11C7/12 ,  G11C7/06 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4094

Abstract: Sense amplifiers and methods for precharging are disclosed, including a sense amplifier having a pair of cross-coupled complementary transistor inverters, and a pair of transistors, each one of the pair of transistors coupled to a respective one of the complementary transistor inverters and a voltage. The sense amplifier further includes a capacitance coupled between the pair of transistors. One method for precharging includes coupling input nodes of the sense amplifier to a precharge voltage, coupling the input nodes of the sense amplifier together, and coupling a resistance to each transistor of a cross-coupled pair to set a voltage threshold (VT) mismatch compensation voltage for each transistor. The voltage difference between the VT mismatch compensation voltage of each transistor is stored.

Abstract translation: 公开了用于预充电的感测放大器和方法，包括具有一对交叉耦合的互补晶体管反相器的读出放大器和一对晶体管，耦合到互补晶体管反相器中的相应一个的一对晶体管中的每一个， 。 感测放大器还包括耦合在该对晶体管之间的电容。 一种用于预充电的方法包括将读出放大器的输入节点耦合到预充电电压，将读出放大器的输入节点耦合在一起，并将电阻耦合到交叉耦合对的每个晶体管，以设置电压阈值（VT）失配补偿 每个晶体管的电压。 存储每个晶体管的VT失配补偿电压之间的电压差。

公开(公告)号：US09082466B2

公开(公告)日：2015-07-14

申请号：US13949006

申请日：2013-07-23

Applicant: Micron Technology, Inc.

Inventor： Zhong-Yi Xia ,  Vikram K. Bollu ,  Jonathan L. Gossi ,  Howard C. Kirsch ,  Todd A. Merritt

IPC: G11C5/14 ,  G11C8/08 ,  G11C16/26 ,  G11C11/16 ,  G11C11/4091

CPC classification number: G11C8/08 ,  G11C11/16 ,  G11C11/4085 ,  G11C11/4091 ,  G11C16/26

Abstract: Apparatuses and methods for adjusting deactivation voltages are described herein. An example apparatus may include a voltage control circuit. The voltage control circuit may be configured to receive an address and to adjust a deactivation voltage of an access line associated with a target group of memory cells from a first voltage to a second voltage based, at least in part, on the address. In some examples, the first voltage may be lower than the second voltage.

Abstract translation: 本文描述了用于调节失活电压的装置和方法。 示例性装置可以包括电压控制电路。 电压控制电路可以被配置为至少部分地基于地址来接收地址并且将与目标存储器单元组相关联的接入线路的从第一电压到第二电压的去激活电压调整。 在一些示例中，第一电压可以低于第二电压。

公开(公告)号：US20150049565A1

公开(公告)日：2015-02-19

申请号：US13970518

申请日：2013-08-19

Applicant: Micron Technology, Inc.

Inventor： Zhong-yi Xia ,  Scott J. Derner ,  Charles L. Ingalls ,  Howard C. Kirsch

IPC: G11C7/06 ,  G11C7/12

CPC classification number: G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C11/4091 ,  G11C16/28

Abstract: Apparatuses, sense amplifier circuits, and methods for operating a sense amplifier circuit in a memory are described. An example apparatus includes a sense amplifier circuit configured to be coupled to a digit line and configured to, during a memory access operation, drive the digit line to a voltage that indicates the logical value of the charge stored by a memory cell coupled to the digit line. During an initial time period of the memory access operation, the sense amplifier circuit is configured to drive the digit line to a first voltage that indicates the logical value of the charge stored by the memory cell. After the initial time period, the sense amplifier circuit is configured to drive the digit line to a second voltage different than the first voltage that indicates the logical value of the charge stored by the memory cell.

Abstract translation: 描述了用于在存储器中操作读出放大器电路的装置，读出放大器电路和方法。 示例性装置包括读出放大器电路，其被配置为耦合到数字线并且被配置为在存储器访问操作期间将数字线驱动到指示由耦合到数字的存储器单元存储的电荷的逻辑值的电压 线。 在存储器访问操作的初始时间周期期间，读出放大器电路被配置为将数字线驱动到指示由存储器单元存储的电荷的逻辑值的第一电压。 在初始时间段之后，读出放大器电路被配置为将数字线驱动到不同于指示由存储器单元存储的电荷的逻辑值的第一电压的第二电压。

公开(公告)号：US20140085992A1

公开(公告)日：2014-03-27

申请号：US14094466

申请日：2013-12-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： J. Wayne Thompson ,  Howard C. Kirsch ,  Charles L. Ingalls

IPC: G11C7/12 ,  G11C7/06

CPC classification number: G11C7/12 ,  G11C7/06 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4094

Abstract: Sense amplifiers and methods for precharging are disclosed, including a sense amplifier having a pair of cross-coupled complementary transistor inverters, and a pair of transistors, each one of the pair of transistors coupled to a respective one of the complementary transistor inverters and a voltage. The sense amplifier further includes a capacitance coupled between the pair of transistors. One method for precharging includes coupling input nodes of the sense amplifier to a precharge voltage, coupling the input nodes of the sense amplifier together, and coupling a resistance to each transistor of a cross-coupled pair to set a voltage threshold (VT) mismatch compensation voltage for each transistor. The voltage difference between the VT mismatch compensation voltage of each transistor is stored.

Abstract translation: 公开了用于预充电的感测放大器和方法，包括具有一对交叉耦合互补晶体管反相器的读出放大器和一对晶体管，耦合到互补晶体管反相器中的相应一个的一对晶体管中的每一个， 。 感测放大器还包括耦合在该对晶体管之间的电容。 一种用于预充电的方法包括将读出放大器的输入节点耦合到预充电电压，将读出放大器的输入节点耦合在一起，并将电阻耦合到交叉耦合对的每个晶体管，以设置电压阈值（VT）失配补偿 每个晶体管的电压。 存储每个晶体管的VT失配补偿电压之间的电压差。

公开(公告)号：US09159392B2

公开(公告)日：2015-10-13

申请号：US14254433

申请日：2014-04-16

Applicant: Micron Technology, Inc.

Inventor： Tae Kim ,  Howard C. Kirsch ,  Charles L. Ingalls ,  Shigeki Tomishima ,  K. Shawn Smith

IPC: G11C5/02 ,  G11C8/08 ,  H01L27/02 ,  H01L27/105 ,  H01L27/108 ,  G11C8/14 ,  H01L27/118

CPC classification number: G11C8/08 ,  G11C5/025 ,  G11C8/14 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11898

Abstract: Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors used to selectively access cells within the array are transistors of a second type, such as n-type transistors. Local word line drivers are coupled to respective word lines extending through the array. Each local word line drivers includes at least one transistor. However, all of the transistors in the local word line drivers are of the second type. A well of semiconductor material of the second type, is also formed in the material of the first type, and a plurality of global word line drivers are formed using the well. Other subsystems and methods are disclosed.

Abstract translation: 存储器子系统和方法，例如涉及形成在第一类型的半导体材料上的存储单元阵列的那些，例如p型衬底。 在至少一个这样的子系统中，用于选择性地访问阵列内的单元的所有晶体管都是第二类型的晶体管，例如n型晶体管。 本地字线驱动器耦合到延伸穿过阵列的相应字线。 每个本地字线驱动器包括至少一个晶体管。 然而，本地字线驱动器中的所有晶体管都是第二类。 第二种类型的半导体材料的阱也形成在第一类型的材料中，并且使用该阱形成多个全局字线驱动器。 公开了其他子系统和方法。

公开(公告)号：US20150029804A1

公开(公告)日：2015-01-29

申请号：US13949006

申请日：2013-07-23

Applicant: Micron Technology, Inc.

Inventor： Zhong-Yi Xia ,  Vikram K. Bollu ,  Jonathan L. Gossi ,  Howard C. Kirsch ,  Todd A. Merritt

IPC: G11C8/08

CPC classification number: G11C8/08 ,  G11C11/16 ,  G11C11/4085 ,  G11C11/4091 ,  G11C16/26

Abstract: Apparatuses and methods for adjusting deactivation voltages are described herein. An example apparatus may include a voltage control circuit. The voltage control circuit may be configured to receive an address and to adjust a deactivation voltage of an access line associated with a target group of memory cells from a first voltage to a second voltage based, at least in part, on the address. In some examples, the first voltage may be lower than the second voltage.

Abstract translation: 本文描述了用于调节失活电压的装置和方法。 示例性装置可以包括电压控制电路。 电压控制电路可以被配置为至少部分地基于地址来接收地址并且将与目标存储器单元组相关联的接入线路的从第一电压到第二电压的去激活电压调整。 在一些示例中，第一电压可以低于第二电压。

公开(公告)号：US20140226427A1

公开(公告)日：2014-08-14

申请号：US14254433

申请日：2014-04-16

Applicant: Micron Technology, Inc.

Inventor： Tae Kim ,  Howard C. Kirsch ,  Charles L. Ingalls ,  Shigeki Tomishima ,  K. Shawn Smith

IPC: G11C8/08

CPC classification number: G11C8/08 ,  G11C5/025 ,  G11C8/14 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11898

Abstract: Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors used to selectively access cells within the array are transistors of a second type, such as n-type transistors. Local word line drivers are coupled to respective word lines extending through the array. Each local word line drivers includes at least one transistor. However, all of the transistors in the local word line drivers are of the second type. A well of semiconductor material of the second type, is also formed in the material of the first type, and a plurality of global word line drivers are formed using the well. Other subsystems and methods are disclosed.

Abstract translation: 存储器子系统和方法，例如涉及形成在第一类型的半导体材料上的存储单元阵列的那些，例如p型衬底。 在至少一个这样的子系统中，用于选择性地访问阵列内的单元的所有晶体管都是第二类型的晶体管，例如n型晶体管。 本地字线驱动器耦合到延伸穿过阵列的相应字线。 每个局部字线驱动器包括至少一个晶体管。 然而，本地字线驱动器中的所有晶体管都是第二类。 第二种类型的半导体材料的阱也形成在第一类型的材料中，并且使用该阱形成多个全局字线驱动器。 公开了其他子系统和方法。

公开(公告)号：US09076501B2

公开(公告)日：2015-07-07

申请号：US13970518

申请日：2013-08-19

Applicant: Micron Technology, Inc.

Inventor： Zhong-yi Xia ,  Scott J. Derner ,  Charles L. Ingalls ,  Howard C. Kirsch

IPC: G11C16/28 ,  G11C7/06 ,  G11C7/12

CPC classification number: G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C11/4091 ,  G11C16/28

Abstract: Apparatuses, sense amplifier circuits, and methods for operating a sense amplifier circuit in a memory are described. An example apparatus includes a sense amplifier circuit configured to be coupled to a digit line and configured to, during a memory access operation, drive the digit line to a voltage that indicates the logical value of the charge stored by a memory cell coupled to the digit line. During an initial time period of the memory access operation, the sense amplifier circuit is configured to drive the digit line to a first voltage that indicates the logical value of the charge stored by the memory cell. After the initial time period, the sense amplifier circuit is configured to drive the digit line to a second voltage different than the first voltage that indicates the logical value of the charge stored by the memory cell.

Abstract translation: 描述了用于在存储器中操作读出放大器电路的装置，读出放大器电路和方法。 示例性装置包括读出放大器电路，其被配置为耦合到数字线并且被配置为在存储器访问操作期间将数字线驱动到指示由耦合到数字的存储器单元存储的电荷的逻辑值的电压 线。 在存储器访问操作的初始时间周期期间，读出放大器电路被配置为将数字线驱动到指示由存储器单元存储的电荷的逻辑值的第一电压。 在初始时间段之后，读出放大器电路被配置为将数字线驱动到不同于指示由存储器单元存储的电荷的逻辑值的第一电压的第二电压。