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    Drain select gate formation methods and apparatus
    1.
    发明授权
    Drain select gate formation methods and apparatus 有权

    公开(公告)号：US10242995B2

    公开(公告)日：2019-03-26

    申请号：US15808468

    申请日：2017-11-09

    Applicant: Micron Technology, Inc.

    Inventor： Hongbin Zhu ,  Lijing Gou ,  Gordon Haller ,  Luan C. Tran

    IPC: H01L27/11556 ,  H01L27/11582 ,  H01L21/3205 ,  H01L21/28 ,  H01L21/306 ,  H01L21/311 ,  H01L21/302

    Abstract: Some embodiments include a string of charge storage devices formed along a vertical channel of semiconductor material; a gate region of a drain select gate (SGD) transistor, the gate region at least partially surrounding the vertical channel; a dielectric barrier formed in the gate region; a first isolation layer formed above the gate region and the dielectric barrier; a drain region of the SGD transistor formed above the vertical channel; and a second isolation layer formed above the first isolation layer and the drain region, wherein the second isolation layer includes a conductive contact in electrical contact with the drain region of the SGD transistor. Additional apparatus and methods are disclosed.

    Reticles, And Methods Of Mitigating Asymmetric Lens Heating In Photolithography
    3.
    发明申请
    Reticles, And Methods Of Mitigating Asymmetric Lens Heating In Photolithography 审中-公开
    网格和减轻光刻中不对称透镜加热的方法

    公开(公告)号：US20150015860A1

    公开(公告)日：2015-01-15

    申请号：US14500625

    申请日：2014-09-29

    Applicant: Micron Technology, Inc.

    Inventor： Scott L. Light ,  Dan Millward ,  Yuan He ,  Kaveri Jain ,  Lijing Gou ,  Zishu Zhang ,  Anton J. deVilliers ,  Michael D. Hyatt ,  Jianming Zhou

    IPC: G03F7/20

    CPC classification number: G03F7/70741 ,  G03F1/38 ,  G03F7/70433 ,  G03F7/70891

    Abstract: A method of mitigating asymmetric lens heating in photolithographically patterning a photo-imageable material using a reticle includes determining where first hot spot locations are expected to occur on a lens when using a reticle to pattern a photo-imageable material. The reticle is then fabricated to include non-printing features within a non-printing region of the reticle which generate additional hot spot locations on the lens when using the reticle to pattern the photo-imageable material. Other implementations are contemplated, including reticles which may be independent of method of use or fabrication.

    Abstract translation: 使用光掩模光刻地图案化可光成像材料的方法来减轻不对称透镜加热的方法包括当使用掩模版图案可光成像材料时，确定预期在透镜上将出现第一热点位置的位置。 然后制造掩模版以在掩模版的非印刷区域内包括非印刷特征，当使用掩模版对可光成像材料进行图案化时，其在透镜上产生额外的热点位置。 考虑了其他实施方式，包括可以独立于使用或制造方法的标线。

    SEMICONDUCTOR DEVICE STRUCTURES
    4.
    发明申请
    SEMICONDUCTOR DEVICE STRUCTURES 有权
    半导体器件结构

    公开(公告)号：US20140353803A1

    公开(公告)日：2014-12-04

    申请号：US14457658

    申请日：2014-08-12

    Applicant: Micron Technology, Inc.

    Inventor： Adam L. Olson ,  Kaveri Jain ,  Lijing Gou ,  William R. Brown ,  Ho Seop Eom ,  Xue Chen ,  Anton J. deVilliers

    IPC: H01L23/52

    CPC classification number: H01L23/528 ,  H01L21/0226 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/441 ,  H01L21/467 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/52 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods of forming features are disclosed. One method comprises forming a resist over a pool of acidic or basic material on a substrate structure, selectively exposing the resist to an energy source to form exposed resist portions and non-exposed resist portions, and diffusing acid or base of the acidic or basic material from the pool into proximal portions of the resist. Another method comprises forming a plurality of recesses in a substrate structure. The plurality of recesses are filled with a pool material comprising acid or base. A resist is formed over the pool material and the substrate structure and acid or base is diffused into adjacent portions of the resist. The resist is patterned to form openings in the resist. The openings comprise wider portions distal to the substrate structure and narrower portions proximal to the substrate structure. Additional methods and semiconductor device structures including the features are disclosed.

    Abstract translation: 公开了形成特征的方法。 一种方法包括在衬底结构上的酸性或碱性材料池上形成抗蚀剂，选择性地将抗蚀剂暴露于能量源以形成暴露的抗蚀剂部分和未曝光的抗蚀剂部分，以及将酸性或碱性材料的酸或碱扩散 从池中到抗蚀剂的近端部分。 另一种方法包括在衬底结构中形成多个凹陷。 多个凹部填充有包含酸或碱的池材料。 在池材料上形成抗蚀剂，并且衬底结构和酸或碱扩散到抗蚀剂的相邻部分。 抗蚀剂被图案化以在抗蚀剂中形成开口。 开口包括远离衬底结构的较宽部分和靠近衬底结构的较窄部分。 公开了包括这些特征的附加方法和半导体器件结构。

    DRAIN SELECT GATE FORMATION METHODS AND APPARATUS
    6.
    发明申请
    DRAIN SELECT GATE FORMATION METHODS AND APPARATUS 有权
    排水选择门形成方法和装置

    公开(公告)号：US20160233225A1

    公开(公告)日：2016-08-11

    申请号：US14619243

    申请日：2015-02-11

    Applicant: Micron Technology, Inc.

    Inventor： Hongbin Zhu ,  Lijing Gou ,  Gordon Haller ,  Luan C. Tran

    IPC: H01L27/115

    CPC classification number: H01L27/11556 ,  H01L27/11582

    Abstract: Some embodiments include a string of charge storage devices formed along a vertical channel of semiconductor material; a gate region of a drain select gate (SGD) transistor, the gate region at least partially surrounding the vertical channel; a dielectric barrier formed in the gate region; a first isolation layer formed above the gate region and the dielectric barrier; a drain region of the SGD transistor formed above the vertical channel; and a second isolation layer formed above the first isolation layer and the drain region, wherein the second isolation layer includes a conductive contact in electrical contact with the drain region of the SGD transistor. Additional apparatus and methods are disclosed.

    Abstract translation: 一些实施例包括沿着半导体材料的垂直沟道形成的一串电荷存储装置; 漏极选择栅极（SGD）晶体管的栅极区域，所述栅极区域至少部分地围绕所述垂直沟道; 在所述栅极区域中形成的介质阻挡层; 形成在所述栅极区域和所述电介质屏障之上的第一隔离层; 形成在垂直沟道上方的SGD晶体管的漏极区域; 以及形成在所述第一隔离层和所述漏极区之上的第二隔离层，其中所述第二隔离层包括与所述SGD晶体管的漏极区域电接触的导电接触。 公开了附加的装置和方法。

    Semiconductor Constructions And Methods Of Forming Patterns
    7.
    发明申请
    Semiconductor Constructions And Methods Of Forming Patterns 有权
    半导体结构和形成方式

    公开(公告)号：US20130302981A1

    公开(公告)日：2013-11-14

    申请号：US13941747

    申请日：2013-07-15

    Applicant: Micron Technology, Inc.

    Inventor： Dan Millward ,  Kaveri Jain ,  Zishu Zhang ,  Lijing Gou ,  Anton J. deVilliers ,  Jianming Zhou ,  Yuan He ,  Michael D. Hyatt ,  Scott L. Light

    IPC: H01L21/768

    CPC classification number: H01L21/76879 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10882 ,  H01L27/10888

    Abstract: Some embodiments include methods of forming patterns. A semiconductor substrate is formed to comprise an electrically insulative material over a set of electrically conductive structures. An interconnect region is defined across the electrically conductive structures, and regions on opposing sides of the interconnect region are defined as secondary regions. A two-dimensional array of features is formed over the electrically insulative material. The two-dimensional array extends across the interconnect region and across the secondary regions. A pattern of the two-dimensional array is transferred through the electrically insulative material of the interconnect region to form contact openings that extend through the electrically insulative material and to the electrically conductive structures, and no portions of the two-dimensional array of the secondary regions is transferred into the electrically insulative material.

    Abstract translation: 一些实施例包括形成图案的方法。 半导体衬底被形成为在一组导电结构之上包括电绝缘材料。 跨导电结构限定互连区域，并且互连区域的相对侧上的区域被定义为次级区域。 特征的二维阵列形成在电绝缘材料上。 二维阵列跨越互连区域并跨越次级区域延伸。 二维阵列的图案通过互连区域的电绝缘材料转移以形成延伸穿过电绝缘材料和导电结构的接触开口，并且二次区域的二维阵列的任何部分 被转移到电绝缘材料中。

    Semiconductor device structures
    9.
    发明授权
    Semiconductor device structures 有权

    公开(公告)号：US10522461B2

    公开(公告)日：2019-12-31

    申请号：US16042255

    申请日：2018-07-23

    Applicant: Micron Technology, Inc.

    Inventor： Adam L. Olson ,  Kaveri Jain ,  Lijing Gou ,  William R. Brown ,  Ho Seop Eom ,  Xue (Gloria) Chen ,  Anton J. deVilliers

    IPC: H01L21/31 ,  H01L23/528 ,  H01L21/467 ,  H01L23/52 ,  H01L21/768 ,  H01L21/027 ,  H01L21/02 ,  H01L21/308

    Abstract: A method of forming a semiconductor structure comprises forming pools of acidic or basic material in a substrate structure. A resist is formed over the pools of acidic or basic material and the substrate structure. The acidic or basic material is diffused from the pools into portions of the resist proximal to the pools more than into portions of the resist distal to the pools. Then, the resist is exposed to a developer to remove a greater amount of the resist portions proximal to the pools compared to the resist portions distal to the pools to form openings in the resist. The openings have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure. The method may further comprise forming features in the openings of the resist. The features have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure.

    Semiconductor device structures
    10.
    发明授权
    Semiconductor device structures 有权

    公开(公告)号：US10032719B2

    公开(公告)日：2018-07-24

    申请号：US15606312

    申请日：2017-05-26

    Applicant: Micron Technology, Inc.

    Inventor： Adam L. Olson ,  Kaveri Jain ,  Lijing Gou ,  William R. Brown ,  Ho Seop Eom ,  Xue (Gloria) Chen ,  Anton J. deVilliers

    IPC: H01L21/31 ,  H01L23/528 ,  H01L21/02 ,  H01L21/027 ,  H01L23/52 ,  H01L21/768 ,  H01L21/308 ,  H01L21/467

    Abstract: A method of forming a semiconductor structure comprises forming pools of acidic or basic material in a substrate structure. A resist is formed over the pools of acidic or basic material and the substrate structure. The acidic or basic material is diffused from the pools into portions of the resist proximal to the pools more than into portions of the resist distal to the pools. Then, the resist is exposed to a developer to remove a greater amount of the resist portions proximal to the pools compared to the resist portions distal to the pools to form openings in the resist. The openings have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure. The method may further comprise forming features in the openings of the resist. The features have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure.

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