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公开(公告)号：US10482954B2
公开(公告)日：2019-11-19
申请号：US15686308
申请日：2017-08-25
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Roberto Bez , Ferdinando Bedeschi , Roberto Gastaldi
Abstract: A phase change memory device with memory cells (2) formed by a phase change memory element (3) and a selection switch (4). A reference cell (2a) formed by an own phase change memory element (3) and an own selection switch (4) is associated to a group (7) of memory cells to be read. An electrical quantity of the group of memory cells is compared with an analogous electrical quantity of the reference cell, thereby compensating any drift in the properties of the memory cells.
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公开(公告)号：US10074419B2
公开(公告)日：2018-09-11
申请号：US15589320
申请日：2017-05-08
Applicant: Micron Technology, Inc.
Inventor： Ferdinando Bedeschi , Roberto Gastaldi
CPC classification number: G11C13/0033 , G06F11/1068 , G11C11/5678 , G11C13/0004 , G11C13/0038 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C14/009 , G11C16/3418 , G11C29/52
Abstract: Methods and systems to refresh a nonvolatile memory device, such as a phase change memory. In an embodiment, as a function of system state, a memory device performs either a first refresh of memory cells using a margined read reference level or a second refresh of error-corrected memory cells using a non-margined read reference level.
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公开(公告)号：US09646689B2
公开(公告)日：2017-05-09
申请号：US14753938
申请日：2015-06-29
Applicant: Micron Technology, Inc.
Inventor： Ferdinando Bedeschi , Roberto Gastaldi
CPC classification number: G11C13/0033 , G06F11/1068 , G11C11/5678 , G11C13/0004 , G11C13/0038 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C14/009 , G11C16/3418 , G11C29/52
Abstract: Methods and systems to refresh a nonvolatile memory device, such as a phase change memory. In an embodiment, as a function of system state, a memory device performs either a first refresh of memory cells using a margined read reference level or a second refresh of error-corrected memory cells using a non-margined read reference level.
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公开(公告)号：US20150255152A1
公开(公告)日：2015-09-10
申请号：US14717784
申请日：2015-05-20
Applicant: Micron Technology, Inc.
Inventor： Ferdinando Bedeschi , Roberto Gastaldi
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C11/1673 , G11C11/1675 , G11C13/0002 , G11C13/0033 , G11C13/0069 , G11C2013/0047 , G11C2013/0057 , G11C2013/0076
Abstract: The present disclosure includes apparatuses and methods for sensing a resistance variable memory cell. A number of embodiments include programming a memory cell to an initial data state and determining a data state of the memory cell by applying a programming signal to the memory cell, the programming signal associated with programming memory cells to a particular data state, and determining whether the data state of the memory cell changes from the initial data state to the particular data state during application of the programming signal.
Abstract translation: 本公开包括用于感测电阻变量存储单元的装置和方法。 多个实施例包括将存储器单元编程为初始数据状态，并通过将编程信号施加到存储器单元，将编程信号与编程存储器单元相关联到特定数据状态来确定存储器单元的数据状态，以及确定是否 在应用编程信号期间，存储单元的数据状态从初始数据状态变为特定数据状态。
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公开(公告)号：US08913426B2
公开(公告)日：2014-12-16
申请号：US13913714
申请日：2013-06-10
Applicant: Micron Technology, Inc.
Inventor： Ferdinando Bedeschi , Roberto Gastaldi
CPC classification number: G11C13/004 , G11C11/5678 , G11C13/0004 , G11C13/0035 , G11C13/0064 , G11C13/0069 , G11C2013/0054 , G11C2211/5634 , G11C2213/54
Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.
Abstract translation: 本文公开的主题涉及存储器件，更具体地涉及写入相变存储器的性能。
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Patent Agency Ranking
公开(公告)号：US20180366189A1
公开(公告)日：2018-12-20
申请号：US16108828
申请日：2018-08-22
Applicant: Micron Technology, Inc.
Inventor： Ferdinando Bedeschi , Roberto Gastaldi
CPC classification number: G11C13/0033 , G06F11/1068 , G11C11/5678 , G11C13/0004 , G11C13/0038 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C14/009 , G11C16/3418 , G11C29/52
Abstract: Methods and systems to refresh a nonvolatile memory device, such as a phase change memory. In an embodiment, as a function of system state, a memory device performs either a first refresh of memory cells using a margined read reference level or a second refresh of error-corrected memory cells using a non-margined read reference level.
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公开(公告)号：US20140036583A1
公开(公告)日：2014-02-06
申请号：US14047605
申请日：2013-10-07
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Roberto Bez , Ferdinando Bedeschi , Roberto Gastaldi
IPC: G11C13/00
CPC classification number: G11C13/0004 , G11C11/56 , G11C11/5678 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2213/79 , H01L27/2427 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144
Abstract: A phase change memory device with memory cells (2) formed by a phase change memory element (3) and a selection switch (4). A reference cell (2a) formed by an own phase change memory element (3) and an own selection switch (4) is associated to a group (7) of memory cells to be read. An electrical quantity of the group of memory cells is compared with an analogous electrical quantity of the reference cell, thereby compensating any drift in the properties of the memory cells.
Abstract translation: 一种具有由相变存储元件（3）和选择开关（4）形成的存储单元（2）的相变存储器件。 由自己的相变存储元件（3）和自己的选择开关（4）形成的参考单元（2a）与待读取的存储单元组（7）相关联。 将该组存储器单元的电量与参考单元的类似电量进行比较，由此补偿存储单元的特性中的任何漂移。
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8.发明申请公开(公告)号：US20190221264A1
公开(公告)日：2019-07-18
申请号：US16362082
申请日：2019-03-22
Applicant: Micron Technology, Inc.
Inventor： Paolo Tessariol , Roberto Gastaldi
CPC classification number: G11C16/0483 , G11C16/10
Abstract: Some embodiments include apparatus and methods having a string of memory cells, a conductive line and a bipolar junction transistor configured to selectively couple the string of memory cells to the conductive line. Other embodiments including additional apparatus and methods are described.
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9.发明授权公开(公告)号：US10269430B2
公开(公告)日：2019-04-23
申请号：US15651985
申请日：2017-07-17
Applicant: Micron Technology, Inc.
Inventor： Paolo Tessariol , Roberto Gastaldi
Abstract: Some embodiments include apparatus and methods having a string of memory cells, a conductive line and a bipolar junction transistor configured to selectively couple the string of memory cells to the conductive line. Other embodiments including additional apparatus and methods are described.
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公开(公告)号：US20170352414A1
公开(公告)日：2017-12-07
申请号：US15686308
申请日：2017-08-25
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Roberto Bez , Ferdinando Bedeschi , Roberto Gastaldi
CPC classification number: G11C13/0004 , G11C11/56 , G11C11/5678 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2213/79 , H01L27/2427 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144
Abstract: A phase change memory device with memory cells (2) formed by a phase change memory element (3) and a selection switch (4). A reference cell (2a) formed by an own phase change memory element (3) and an own selection switch (4) is associated to a group (7) of memory cells to be read. An electrical quantity of the group of memory cells is compared with an analogous electrical quantity of the reference cell, thereby compensating any drift in the properties of the memory cells.
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