-
公开(公告)号：US11947672B2
公开(公告)日：2024-04-02
申请号：US17189329
申请日：2021-03-02
Applicant: NXP B.V.
Inventor： Andreas Bernardus Maria Jansman , Andreas Lentz
CPC classification number: G06F21/567 , G06F1/28 , G06F1/3296 , G06F21/81 , H03K3/0315 , H03K3/037 , H03K21/02 , G06F2221/034
Abstract: A voltage glitch detector includes a ring oscillator, a plurality of counters, a combined result circuit, and a result evaluation circuit. The ring oscillator includes a plurality of series-connected stages. An output of a last stage of the ring oscillator is coupled to an input of a first stage of the ring oscillator. Each counter of the plurality of counters has an input coupled to a node located between two stages of the plurality of series-connected stages. The combined result circuit is coupled to each of the plurality of counters. The combined result circuit combines the count values received from each counter of the plurality of counters to provide a combined result. The result evaluation circuit is coupled to compare the combined result with a reference value to determine when a voltage glitch is detected.
-
公开(公告)号：US09318997B2
公开(公告)日：2016-04-19
申请号：US14034398
申请日：2013-09-23
Applicant: NXP B.V.
CPC classification number: H03B1/00 , H03B5/30 , H03B2202/00 , H03H9/00 , H03H9/02338 , H03H9/02433 , H03H9/2452 , H03H2009/02307 , H03H2009/02456 , H03H2009/02496
Abstract: A resonator has a main resonator body and a secondary resonator structure. The resonator body has a desired mode of vibration of the resonator alone, and a parasitic mode of vibration, wherein the parasitic mode comprises vibration of the resonator body and the secondary resonator structure as a composite body. In this way, unwanted vibrational modes are quenched by the second suspended body.
Abstract translation: 谐振器具有主谐振器体和次谐振器结构。 谐振器本体具有谐振器单独的期望的振动模式和寄生振动模式，其中寄生模式包括作为复合体的谐振器体和辅助谐振器结构的振动。 以这种方式，不需要的振动模式被第二悬挂体淬火。
-
公开(公告)号：US20160020296A1
公开(公告)日：2016-01-21
申请号：US14714927
申请日：2015-05-18
Applicant: NXP B.V.
Inventor： Godefridus Adrianus Maria Hurkx , Jeroen Antoon Croon , Johannes Josephus Theodorus Marinus Donkers , Jan Sonsky , Stephen John Sque , Andreas Bernardus Maria Jansman , Markus Mueller , Stephan Heil , Tim Boettcher
CPC classification number: H01L29/475 , H01L21/02362 , H01L21/0254 , H01L29/2003 , H01L29/401 , H01L29/417 , H01L29/42316 , H01L29/7787 , H01L29/7788 , H01L29/872
Abstract: Disclosed is a semiconductor device comprising a group 13 nitride heterojunction comprising a first layer having a first bandgap and a second layer having a second bandgap, wherein the first layer is located between a substrate and the second layer; and a Schottky electrode and a first further electrode each conductively coupled to a different area of the heterojunction, said Schottky electrode comprising a central region and an edge region, wherein the element comprises a conductive barrier portion located underneath said edge region only of the Schottky electrode for locally increasing the Schottky barrier of the Schottky electrode. A method of manufacturing such a semiconductor device is also disclosed.
-
4.发明授权Heterojunction semiconductor device with conductive barrier portion and manufacturing method 有权具有导电阻挡部分的异质结半导体器件及制造方法公开(公告)号：US09064847B2
公开(公告)日：2015-06-23
申请号：US13895228
申请日：2013-05-15
Applicant: NXP B.V.
Inventor： Godefridus Andrianus Maria Hurkx , Jeroen Antoon Croon , Johannes Josephus Theodorus Marinus Donkers , Jan Sonsky , Stephen John Sque , Andreas Bernardus Maria Jansman , Markus Mueller , Stephan Heil , Tim Boettcher
IPC: H01L29/47 , H01L29/417 , H01L29/423 , H01L29/778 , H01L29/872 , H01L29/40 , H01L21/02 , H01L29/20
CPC classification number: H01L29/475 , H01L21/02362 , H01L21/0254 , H01L29/2003 , H01L29/401 , H01L29/417 , H01L29/42316 , H01L29/7787 , H01L29/7788 , H01L29/872
Abstract: Disclosed is a semiconductor device comprising a group 13 nitride heterojunction comprising a first layer having a first bandgap and a second layer having a second bandgap, wherein the first layer is located between a substrate and the second layer; and a Schottky electrode and a first further electrode each conductively coupled to a different area of the heterojunction, said Schottky electrode comprising a central region and an edge region, wherein the element comprises a conductive barrier portion located underneath said edge region only of the Schottky electrode for locally increasing the Schottky barrier of the Schottky electrode. A method of manufacturing such a semiconductor device is also disclosed.
Abstract translation: 公开了一种包括13族氮化物异质结的半导体器件，其包括具有第一带隙的第一层和具有第二带隙的第二层，其中第一层位于衬底和第二层之间; 以及肖特基电极和第一另外的电极，每个导体耦合到所述异质结的不同区域，所述肖特基电极包括中心区域和边缘区域，其中所述元件包括仅位于所述肖特基电极的所述边缘区域下方的导电阻挡部分 用于局部增加肖特基电极的肖特基势垒。 还公开了制造这种半导体器件的方法。
-
公开(公告)号：US09349819B2
公开(公告)日：2016-05-24
申请号：US14714927
申请日：2015-05-18
Applicant: NXP B.V.
Inventor： Godefridus Adrianus Maria Hurkx , Jeroen Antoon Croon , Johannes Josephus Theodorus Marinus Donkers , Jan Sonsky , Stephen John Sque , Andreas Bernardus Maria Jansman , Markus Mueller , Stephan Heil , Tim Boettcher
IPC: H01L29/20 , H01L21/02 , H01L29/47 , H01L29/417 , H01L29/423 , H01L29/778 , H01L29/872 , H01L29/40
CPC classification number: H01L29/475 , H01L21/02362 , H01L21/0254 , H01L29/2003 , H01L29/401 , H01L29/417 , H01L29/42316 , H01L29/7787 , H01L29/7788 , H01L29/872
Abstract: Disclosed is a semiconductor device comprising a group 13 nitride heterojunction comprising a first layer having a first bandgap and a second layer having a second bandgap, wherein the first layer is located between a substrate and the second layer; and a Schottky electrode and a first further electrode each conductively coupled to a different area of the heterojunction, said Schottky electrode comprising a central region and an edge region, wherein the element comprises a conductive barrier portion located underneath said edge region only of the Schottky electrode for locally increasing the Schottky barrier of the Schottky electrode. A method of manufacturing such a semiconductor device is also disclosed.
Abstract translation: 公开了一种包括13族氮化物异质结的半导体器件，其包括具有第一带隙的第一层和具有第二带隙的第二层，其中第一层位于衬底和第二层之间; 以及肖特基电极和第一另外的电极，每个导体耦合到所述异质结的不同区域，所述肖特基电极包括中心区域和边缘区域，其中所述元件包括仅位于所述肖特基电极的所述边缘区域下方的导电阻挡部分 用于局部增加肖特基电极的肖特基势垒。 还公开了制造这种半导体器件的方法。
-
Patent Agency Ranking
公开(公告)号：US20140176246A1
公开(公告)日：2014-06-26
申请号：US14034398
申请日：2013-09-23
Applicant: NXP B.V.
IPC: H03B1/00
CPC classification number: H03B1/00 , H03B5/30 , H03B2202/00 , H03H9/00 , H03H9/02338 , H03H9/02433 , H03H9/2452 , H03H2009/02307 , H03H2009/02456 , H03H2009/02496
Abstract: A resonator has a main resonator body and a secondary resonator structure. The resonator body has a desired mode of vibration of the resonator alone, and a parasitic mode of vibration, wherein the parasitic mode comprises vibration of the resonator body and the secondary resonator structure as a composite body. In this way, unwanted vibrational modes are quenched by the second suspended body.
Abstract translation: 谐振器具有主谐振器体和次谐振器结构。 谐振器本体具有谐振器单独的期望的振动模式和寄生振动模式，其中寄生模式包括作为复合体的谐振器体和辅助谐振器结构的振动。 以这种方式，不需要的振动模式被第二悬挂体淬火。
-
公开(公告)号：US11474130B2
公开(公告)日：2022-10-18
申请号：US16908338
申请日：2020-06-22
Applicant: NXP B.V.
Inventor： Andreas Lentz , Andreas Bernardus Maria Jansman
IPC: G01R19/165 , G06K19/073 , H03K5/1252
Abstract: An integrated circuit for hardware security comprises a voltage glitch detection processing system comprising an oscillator circuit that generates and outputs a local oscillator clock which is a function of a supply voltage; a counter clocked by the oscillator circuit to generate at least one count value; and a capture section that synchronizes the at least one count value into a system clock domain for detecting a voltage glitch in the supply voltage.
-
公开(公告)号：US10250258B2
公开(公告)日：2019-04-02
申请号：US15279356
申请日：2016-09-28
Applicant: NXP B.V.
IPC: H03K19/003 , H01L23/00 , H01L29/861 , H01L27/06 , G06F21/75 , H01L29/06
Abstract: Embodiments of devices and method for detecting semiconductor substrate thickness are disclosed. In an embodiment, an IC device includes a semiconductor substrate, a charge emitter embedded in the semiconductor substrate and configured to produce an electrical charge in the semiconductor substrate and a charge sensor embedded in the semiconductor substrate and configured to generate a response signal in response to the electrical charge produced in the semiconductor substrate. The magnitude of the response signal depends on the thickness of the semiconductor substrate.
-
公开(公告)号：US20180091147A1
公开(公告)日：2018-03-29
申请号：US15279356
申请日：2016-09-28
Applicant: NXP B.V.
IPC: H03K19/003 , H01L23/00 , H01L29/861 , H01L29/73 , H01L27/06
CPC classification number: H03K19/003 , G06F21/75 , H01L22/34 , H01L23/573 , H01L23/576 , H01L27/0647 , H01L29/0649 , H01L29/861 , H01L29/8611 , H01L29/8613
Abstract: Embodiments of devices and method for detecting semiconductor substrate thickness are disclosed. In an embodiment, an IC device includes a semiconductor substrate, a charge emitter embedded in the semiconductor substrate and configured to produce an electrical charge in the semiconductor substrate and a charge sensor embedded in the semiconductor substrate and configured to generate a response signal in response to the electrical charge produced in the semiconductor substrate. The magnitude of the response signal depends on the thickness of the semiconductor substrate.
-
公开(公告)号：US20210396789A1
公开(公告)日：2021-12-23
申请号：US16908338
申请日：2020-06-22
Applicant: NXP B.V.
Inventor： Andreas Lentz , Andreas Bernardus Maria Jansman
IPC: G01R19/165 , H03K5/1252 , G06K19/073
Abstract: An integrated circuit for hardware security comprises a voltage glitch detection processing system comprising an oscillator circuit that generates and outputs a local oscillator clock which is a function of a supply voltage; a counter clocked by the oscillator circuit to generate at least one count value; and a capture section that synchronizes the at least one count value into a system clock domain for detecting a voltage glitch in the supply voltage.
-
-
-
-
-
-
-
-
-
Search Results
10
records
(took 0.016 seconds)
