中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

14 records (took 0.014 seconds)

    INTEGRATED CIRCUIT DEVICE AND METHOD FOR APPLYING ERROR CORRECTION TO SRAM MEMORY
    2.
    发明申请
    INTEGRATED CIRCUIT DEVICE AND METHOD FOR APPLYING ERROR CORRECTION TO SRAM MEMORY 审中-公开
    集成电路装置及其应用于SRAM存储器的错误校正方法

    公开(公告)号：US20170039104A1

    公开(公告)日：2017-02-09

    申请号：US14820436

    申请日：2015-08-06

    Applicant: NXP B.V.

    Inventor： Ajay Kapoor ,  Nur Engin ,  Steven Thoen ,  Jose Pineda de Gyvez

    IPC: G06F11/10 ,  H03M13/35 ,  G11C29/52

    CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G11C29/52 ,  H03M13/353

    Abstract: In accordance with an embodiment of the invention, an integrated circuit (IC) device is disclosed. In the embodiment, the IC device includes an SRAM module, wrapper logic coupled to the SRAM module, a context source, and an ECC profile controller coupled to the context source and to the wrapper logic, the ECC profile controller configured to select an ECC profile in response to context information received from the context source for use by the wrapper logic.

    Abstract translation: 根据本发明的一个实施例，公开了一种集成电路（IC）装置。 在该实施例中，IC器件包括SRAM模块，耦合到SRAM模块的封装逻辑，上下文源以及耦合到上下文源和封装逻辑的ECC简档控制器，ECC简档控制器被配置为选择ECC简档 响应于从上下文源接收的用于由包装器逻辑使用的上下文信息。

    WIRELESS POWER DELIVERY AND DATA LINK
    5.
    发明申请
    WIRELESS POWER DELIVERY AND DATA LINK 有权
    无线电力传输和数据链路

    公开(公告)号：US20150318896A1

    公开(公告)日：2015-11-05

    申请号：US14569024

    申请日：2014-12-12

    Applicant: NXP B.V.

    Inventor： Anthony Kerselaers ,  Liesbeth Gommë ,  Steven Thoen ,  Johan Van Ginderdeuren

    IPC: H04B5/00 ,  H02J5/00

    CPC classification number: H04B5/0037 ,  A61B5/002 ,  G08C17/02 ,  G08C17/04 ,  H02J5/005 ,  H02J7/025 ,  H02J50/12 ,  H04B5/0012 ,  H04B5/0081 ,  H04B5/0093 ,  H04B5/02 ,  H04B13/005

    Abstract: An electromagnetic induction wireless transceiver system including: a magnetic antenna; an electric antenna including first and second plates, the first plate being connectable to a body; and a power driver configured to produce a modulating signal used to drive the magnetic antenna and the electric antenna to produce electromagnetic induction fields, wherein the transceiver when connected to a body in a first location is configured to transmit power to a second electromagnetic induction wireless transceiver connected to a second location a distance from the first location, wherein the first and second locations are connected through magnetic and electric near-field coupling.

    Abstract translation: 一种电磁感应无线收发系统，包括：磁性天线; 包括第一和第二板的电天线，所述第一板可连接到主体; 以及功率驱动器，其被配置为产生用于驱动所述磁性天线和所述电天线以产生电磁感应场的调制信号，其中所述收发器在连接到第一位置中的主体时被配置为向第二电磁感应无线收发器 连接到距离第一位置一定距离的第二位置，其中第一和第二位置通过磁和电近场耦合连接。

    Wireless power delivery and data link
    7.
    发明授权
    Wireless power delivery and data link 有权

    公开(公告)号：US09960815B2

    公开(公告)日：2018-05-01

    申请号：US14569024

    申请日：2014-12-12

    Applicant: NXP B.V.

    Inventor： Anthony Kerselaers ,  Liesbeth Gommë ,  Steven Thoen ,  Johan Van Ginderdeuren

    IPC: H04B5/00 ,  H02J5/00 ,  G08C17/04 ,  H04B5/02 ,  H04B13/00 ,  G08C17/02 ,  H02J50/12 ,  H02J7/02 ,  A61B5/00

    Abstract: An electromagnetic induction wireless transceiver system including: a magnetic antenna; an electric antenna including first and second plates, the first plate being connectable to a body; and a power driver configured to produce a modulating signal used to drive the magnetic antenna and the electric antenna to produce electromagnetic induction fields, wherein the transceiver when connected to a body in a first location is configured to transmit power to a second electromagnetic induction wireless transceiver connected to a second location a distance from the first location, wherein the first and second locations are connected through magnetic and electric near-field coupling.

    Sleep mode operation for volatile memory circuits
    8.
    发明授权
    Sleep mode operation for volatile memory circuits 有权

    公开(公告)号：US09703632B2

    公开(公告)日：2017-07-11

    申请号：US14535970

    申请日：2014-11-07

    Applicant: NXP B.V.

    Inventor： Steven Thoen

    IPC: G11C29/00 ,  G06F11/10 ,  G06F1/32

    CPC classification number: G06F11/1076 ,  G06F1/3296 ,  G06F11/106

    Abstract: Aspects of the present disclosure are directed to circuits, apparatuses and methods for operating volatile memory circuits. According to an example embodiment, an apparatus includes a volatile memory circuit and a control circuit coupled to the volatile memory circuit. The control circuit is configured to generate and store parity data for data blocks written to the volatile memory circuit. The control circuit places the volatile memory circuit in a sleep mode in response to a first control signal. In response to a second control signal, the control circuit places the volatile memory into an active mode. In further response to the second control signal the control circuit detects and corrects errors in the data blocks stored in the volatile memory using the stored parity data.

    SLEEP MODE OPERATION FOR VOLATILE MEMORY CIRCUITS
    9.
    发明申请
    SLEEP MODE OPERATION FOR VOLATILE MEMORY CIRCUITS 有权
    休闲模式操作用于易失性存储器电路

    公开(公告)号：US20160132391A1

    公开(公告)日：2016-05-12

    申请号：US14535970

    申请日：2014-11-07

    Applicant: NXP B.V.

    Inventor： Steven Thoen

    IPC: G06F11/10 ,  G06F1/32

    CPC classification number: G06F11/1076 ,  G06F1/3296 ,  G06F11/106

    Abstract: Aspects of the present disclosure are directed to circuits, apparatuses and methods for operating volatile memory circuits. According to an example embodiment, an apparatus includes a volatile memory circuit and a control circuit coupled to the volatile memory circuit. The control circuit is configured to generate and store parity data for data blocks written to the volatile memory circuit. The control circuit places the volatile memory circuit in a sleep mode in response to a first control signal. In response to a second control signal, the control circuit places the volatile memory into an active mode. In further response to the second control signal the control circuit detects and corrects errors in the data blocks stored in the volatile memory using the stored parity data.

    Abstract translation: 本公开的方面涉及用于操作易失性存储器电路的电路，装置和方法。 根据示例实施例，一种装置包括易失性存储器电路和耦合到易失性存储器电路的控制电路。 控制电路被配置为产生并存储写入易失性存储器电路的数据块的奇偶校验数据。 响应于第一控制信号，控制电路使易失性存储器电路处于睡眠模式。 响应于第二控制信号，控制电路将易失性存储器置于活动模式。 为了进一步响应第二控制信号，控制电路使用存储的奇偶校验数据来检测和校正存储在易失性存储器中的数据块中的错误。

Patent Agency Ranking