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1.发明授权Method and apparatus for memory access scheduling to reduce memory access latency 有权用于存储器访问调度以减少存储器访问延迟的方法和装置公开(公告)号：US06785793B2
公开(公告)日：2004-08-31
申请号：US09966957
申请日：2001-09-27
IPC分类号： G06F1200
CPC分类号： G06F12/0215 , G06F13/161 , G06F13/1631
摘要： A device is presented including a memory controller. The memory controller is connected to a read request queue. A command queue is coupled to the memory controller. A memory page table is connected to the memory controller. The memory page table has many page table entries. A memory page history table is connected to the memory controller. The memory history table has many page history table entries. A pre-calculated lookup table is connected to the memory controller. The memory controller includes a memory scheduling process to reduce memory access latency.
摘要翻译： 呈现包括存储器控制器的设备。 存储器控制器连接到读请求队列。 命令队列耦合到存储器控制器。 存储器页表连接到存储器控制器。 内存页表具有许多页表条目。 存储器页历史表连接到存储器控制器。 内存历史表有许多页历史表条目。 预先计算的查找表连接到存储器控制器。 存储器控制器包括用于减少存储器访问延迟的存储器调度处理。
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公开(公告)号：US07127574B2
公开(公告)日：2006-10-24
申请号：US10692245
申请日：2003-10-22
IPC分类号： G06F12/02
CPC分类号： G06F13/1631
摘要： Embodiments of the present invention provide an algorithm for scheduling read and write transactions to memory out of order to improve command and data bus utilization and gain performance over a range of workloads. In particular, memory transactions are sorted into queues so that they do not have page conflict with each other and are scheduled from these queues out of order in accordance with read and write scheduling algorithms to optimize latency.
摘要翻译： 本发明的实施例提供了一种用于将读取和写入事务调度到存储器的算法，以改进命令和数据总线利用率并在一系列工作负载上获得性能的算法。 特别地，存储器事务被排序成队列，使得它们不具有彼此的页冲突，并且根据读和写调度算法从这些队列排序排序以优化等待时间。
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公开(公告)号：US06792496B2
公开(公告)日：2004-09-14
申请号：US09922235
申请日：2001-08-02
申请人： Nagi Aboulenein , Randy B. Osborne
发明人： Nagi Aboulenein , Randy B. Osborne
IPC分类号： G06F1200
CPC分类号： G06F13/4031 , G06F12/0862 , G06F2212/1024
摘要： Prefetching data includes issuing a first request to prefetch data from a memory, receiving a response to the first request from the memory, obtaining a measure of latency between the first request and the response, and controlling issuance of a subsequent request to prefetch other data from the memory based on the measure.
摘要翻译： 预取数据包括发出第一请求以从存储器预取数据，从存储器接收对第一请求的响应，获得第一请求和响应之间的等待时间的度量，以及控制发送后续请求以从其中取出其他数据 基于测量的记忆。
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公开(公告)号：US20050091460A1
公开(公告)日：2005-04-28
申请号：US10692245
申请日：2003-10-22
申请人： Hemant Rotithor , Randy Osborne , Nagi Aboulenein
发明人： Hemant Rotithor , Randy Osborne , Nagi Aboulenein
CPC分类号： G06F13/1631
摘要： Embodiments of the present invention provide an algorithm for scheduling read and write transactions to memory out of order to improve command and data bus utilization and gain performance over a range of workloads. In particular, memory transactions are sorted into queues so that they do not have page conflict with each other and are scheduled from these queues out of order in accordance with read and write scheduling algorithms to optimize latency.
摘要翻译： 本发明的实施例提供了一种用于将读取和写入事务调度到存储器的算法，以改进命令和数据总线利用率并在一系列工作负载上获得性能的算法。 特别地，存储器事务被排序成队列，使得它们不具有彼此的页冲突，并且根据读和写调度算法从这些队列排序排序以优化等待时间。
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公开(公告)号：US08683096B2
公开(公告)日：2014-03-25
申请号：US13535278
申请日：2012-06-27
IPC分类号： G06F3/00
CPC分类号： G06F13/1689 , G06F13/1684 , G11C7/1069 , G11C7/1072 , G11C7/1093 , G11C7/22 , G11C2207/2281 , G11C2207/229 , Y02D10/14
摘要： Disclosed embodiments may include a circuit having a plurality of data terminals, no more than two pairs of differential data strobe terminals associated with the plurality of data terminals, and digital logic circuitry. The digital logic circuitry may be coupled to the data terminals and configured to use the no more than two pairs of differential data strobe terminals concurrently with the plurality of data terminals to transfer data. Other embodiments may be disclosed.
摘要翻译： 公开的实施例可以包括具有多个数据终端的电路，与多个数据终端相关联的不超过两对差分数据选通端子和数字逻辑电路。 数字逻辑电路可以耦合到数据终端，并被配置为与多个数据终端同时使用不超过两对差分数据选通端子来传送数据。 可以公开其他实施例。
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公开(公告)号：US20140003169A1
公开(公告)日：2014-01-02
申请号：US13535278
申请日：2012-06-27
IPC分类号： G11C7/00
CPC分类号： G06F13/1689 , G06F13/1684 , G11C7/1069 , G11C7/1072 , G11C7/1093 , G11C7/22 , G11C2207/2281 , G11C2207/229 , Y02D10/14
摘要： Disclosed embodiments may include a circuit having a plurality of data terminals, no more than two pairs of differential data strobe terminals associated with the plurality of data terminals, and digital logic circuitry. The digital logic circuitry may be coupled to the data terminals and configured to use the no more than two pairs of differential data strobe terminals concurrently with the plurality of data terminals to transfer data. Other embodiments may be disclosed.
摘要翻译： 公开的实施例可以包括具有多个数据终端的电路，与多个数据终端相关联的不超过两对差分数据选通端子和数字逻辑电路。 数字逻辑电路可以耦合到数据终端，并被配置为与多个数据终端同时使用不超过两对差分数据选通端子来传送数据。 可以公开其他实施例。
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公开(公告)号：US20110113199A1
公开(公告)日：2011-05-12
申请号：US12614619
申请日：2009-11-09
CPC分类号： G06F12/0862 , G06F15/8069 , G06F2212/502 , Y02D10/13
摘要： An apparatus and method is described herein for optimization to prefetch throttling, which potentially enhances performance, reduces power consumption, and maintains positive gain for workloads that benefit from prefetching. More specifically, the optimizations described herein allow for bandwidth congestion and prefetch accuracy to be taken into account as feedbacks for throttling at the source of prefetch generation. As a result, when there is low congestion, full prefetch generation is allowed, even if the prefetch is inaccurate, since there is available bandwidth. However, when congestion is high, the determination of throttling falls to prefetch accuracy. If accuracy is high—miss rate is low—then less throttling is needed, because the prefetches are being utilized—performance is being enhanced. Yet, if prefetch accuracy is low—miss rate is high—then more prefetch throttling is needed to save power, because the prefetch are not being utilized—performance is not being enhanced by the large number of prefetches.
摘要翻译： 本文描述了用于优化预取节流的装置和方法，其潜在地增强了性能，降低了功耗，并为从预取中受益的工作负载保持了正增益。 更具体地说，这里描述的优化允许考虑带宽拥塞和预取精度作为用于在预取生成源处节流的反馈。 结果，当拥塞低时，即使预取不准确，由于存在可用带宽，因此允许完全预取生成。 然而，当拥塞较高时，节流的确定下降到预取精度。 如果精度高，错失率低，则需要较少的节流，因为预取已被利用 - 性能正在提高。 然而，如果预取精度低错过率高，则需要更多的预取节流来节省功率，因为预取不被利用 - 性能并没有被大量预取提高。
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公开(公告)号：US20080162799A1
公开(公告)日：2008-07-03
申请号：US11648483
申请日：2006-12-28
申请人： Bryan Spry , Nagi Aboulenein , Steve Kulick
发明人： Bryan Spry , Nagi Aboulenein , Steve Kulick
IPC分类号： G06F13/14
CPC分类号： G06F13/1642
摘要： According to one embodiment, a memory controller is disclosed. The memory controller includes a scheduler to schedule memory transactions to the DIMM and a write address queue to accumulate the write requests while the memory controller is operating in a first mode and to release the write requests to the scheduler whenever the memory controller is operating in a second mode.
摘要翻译： 根据一个实施例，公开了一种存储器控制器。 存储器控制器包括调度器，用于在存储器控制器以第一模式操作时调度到DIMM的存储器事务和写入地址队列以累积写请求，并且每当存储器控制器在 第二模式。
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9.发明申请DYNAMIC POWER MEASUREMENT AND ESTIMATION TO IMPROVE MEMORY SUBSYSTEM POWER PERFORMANCE 有权动态功率测量和估计提高记忆子系统功率性能公开(公告)号：US20150185797A1
公开(公告)日：2015-07-02
申请号：US14142808
申请日：2013-12-28
申请人： Lawrence A. Cooper , Justin J. Song , Xiuting C. Man , Nagi Aboulenein , Christopher E. Cox , Rebecca Z. Loop
发明人： Lawrence A. Cooper , Justin J. Song , Xiuting C. Man , Nagi Aboulenein , Christopher E. Cox , Rebecca Z. Loop
IPC分类号： G06F1/26
CPC分类号： G06F1/28 , G06F1/32 , G06F1/3225 , G06F1/324 , G06F1/3275 , G06F1/3296 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： Dynamic monitoring of current draw by a memory device or memory subsystem can enable a power management system to adjust a memory access performance parameter based on monitored power usage. The system can generate a power usage characterization for the memory device and/or memory subsystem based on monitoring current draw for a known pattern, and then subsequently use the power usage characterization to determine how to adjust the memory access performance parameter.
摘要翻译： 通过存储器设备或存储器子系统对电流消耗的动态监控可以使得电力管理系统能够基于监视的功率使用来调整存储器访问性能参数。 该系统可以基于对已知模式的监测电流消耗来产生用于存储器件和/或存储器子系统的功率使用特征，然后随后使用功率使用表征来确定如何调整存储器访问性能参数。
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公开(公告)号：US20140317343A1
公开(公告)日：2014-10-23
申请号：US14182053
申请日：2014-02-17
CPC分类号： G06F13/1689 , G06F13/1684 , G11C7/1069 , G11C7/1072 , G11C7/1093 , G11C7/22 , G11C2207/2281 , G11C2207/229 , Y02D10/14
摘要： Disclosed embodiments may include a circuit having a plurality of data terminals, no more than two pairs of differential data strobe terminals associated with the plurality of data terminals, and digital logic circuitry. The digital logic circuitry may be coupled to the data terminals and configured to use the no more than two pairs of differential data strobe terminals concurrently with the plurality of data terminals to transfer data. Other embodiments may be disclosed.
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