中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

156 records (took 0.039 seconds)

    Selective fabrication of high capacitance density areas in a low dielectric constant material
    1.
    发明授权
    Selective fabrication of high capacitance density areas in a low dielectric constant material 有权
    在低介电常数材料中选择性地制造高电容密度区域

    公开(公告)号：US07109125B1

    公开(公告)日：2006-09-19

    申请号：US10995762

    申请日：2004-11-22

    Applicant: Q. Z. Liu ,  David Feiler ,  Bin Zhao ,  Phil N. Sherman ,  Maureen Brongo

    Inventor： Q. Z. Liu ,  David Feiler ,  Bin Zhao ,  Phil N. Sherman ,  Maureen Brongo

    IPC: H01L21/302 ,  H01L21/461 ,  H01L21/20 ,  H01L21/8242

    CPC classification number: H01L28/86 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Method for selective fabrication of high capacitance density areas in a low dielectric constant material and related structure are disclosed. In one embodiment, a first area of a dielectric layer is covered, for example with photoresist, while a second area of the dielectric layer is exposed to a dielectric conversion source such as E-beams, I-beams, oxygen plasma, or an appropriate chemical. The exposure causes the dielectric constant of the dielectric layer in the second area to increase. A number of capacitor trenches are etched in the second area of the dielectric. The capacitor trenches are then filled with an appropriate metal, such as copper, and a chemical mechanical polish is performed. The second area in which the capacitor trenches have been etched and filled has a higher capacitance density relative to the first area. In another embodiment, the exposure to the dielectric conversion source is not performed until after the chemical mechanical polish has been performed. In yet another embodiment, a blanket layer of metal, such as aluminum, is first deposited. The blanket layer of metal is then etched to form metal lines. Then a gap fill dielectric is utilized to fill the gaps between the remaining metal lines. A first area of the gap fill dielectric is then covered and a second area of the gap fill dielectric is exposed to a dielectric conversion source. After exposure to the dielectric conversion source, the dielectric constant of the gap fill dielectric in the second area increases. The metal lines in the second area can then be used as capacitor electrodes of a high density capacitor.

    Abstract translation: 公开了用于选择性地制造低介电常数材料和相关结构中的高电容密度区域的方法。 在一个实施例中，电介质层的第一区域例如被光致抗蚀剂覆盖，而介电层的第二区域暴露于电介质转换源（例如电子束，I型波束，氧等离子体）或适当的 化学品。 曝光导致第二区域中介电层的介电常数增加。 在电介质的第二区域中蚀刻多个电容器沟槽。 然后用适当的金属（例如铜）填充电容器沟槽，并进行化学机械抛光。 其中电容器沟槽被蚀刻和填充的第二区域相对于第一区域具有较高的电容密度。 在另一个实施例中，直到进行化学机械抛光之后，不进行介电转换源的曝光。 在又一实施例中，首先沉积诸如铝的金属覆盖层。 然后蚀刻金属覆盖层以形成金属线。 然后使用间隙填充电介质来填充剩余金属线之间的间隙。 然后覆盖间隙填充电介质的第一区域，并且间隙填充电介质的第二区域暴露于电介质转换源。 在暴露于电介质转换源之后，第二区域中间隙填充电介质的介电常数增加。 然后可以将第二区域中的金属线用作高密度电容器的电容器电极。

    Method for fabrication of on-chip inductors and related structure
    2.
    发明授权
    Method for fabrication of on-chip inductors and related structure 有权
    片上电感器制造方法及相关结构

    公开(公告)号：US06309922B1

    公开(公告)日：2001-10-30

    申请号：US09627505

    申请日：2000-07-28

    Applicant: Q. Z. Liu ,  Bin Zhao ,  David Howard

    Inventor： Q. Z. Liu ,  Bin Zhao ,  David Howard

    IPC: H01L218234

    CPC classification number: H01L28/10 ,  H01L27/08

    Abstract: Method for fabrication of on-chip inductors and related structure are disclosed. According to one embodiment, inductors are formed by patterning conductors within a certain dielectric layer in a semiconductor die. Thereafter, the entire dielectric layer in the semiconductor die is subjected to a blanket implantation or sputtering of high permeability material. According to another embodiment, a first area in a semiconductor die is covered, for example, with photoresist. A second area in the semiconductor die includes a patterned conductor which is to be used as an inductor. The patterned conductor is also covered, for example, with photoresist. The second area, excluding the covered patterned conductor is subjected to implantation or sputtering of high permeability material. According to yet another embodiment, a first area of a semiconductor die is covered, for example, with photoresist. A second area in the semiconductor area includes a patterned conductor which is to be used as an inductor. This second area, including the patterned conductor, is subjected to implantation or sputtering of high permeability material. The implantation or sputtering of high permeability materials result in the inductors having much higher inductance values than they would otherwise have.

    Abstract translation: 公开了片上电感器的制造方法和相关结构。 根据一个实施例，电感器通过在半导体管芯内的某个介电层内图案化导体而形成。 此后，对半导体管芯中的整个电介质层进行高导磁率材料的覆盖注入或溅射。 根据另一实施例，半导体管芯中的第一区域例如被光致抗蚀剂覆盖。 半导体管芯中的第二区域包括用作电感器的图案化导体。 图案化的导体也例如用光致抗蚀剂覆盖。 不包括覆盖图案导体的第二区域经受高磁导率材料的注入或溅射。 根据另一个实施例，半导体管芯的第一区域例如被光致抗蚀剂覆盖。 半导体区域中的第二区域包括用作电感器的图案化导体。 包括图案化导体的该第二区域经受高磁导率材料的注入或溅射。 高磁导率材料的注入或溅射导致电感器的电感值高于原来的电感值。

    Method for fabricating on-chip inductors and related structure
    3.
    发明授权
    Method for fabricating on-chip inductors and related structure 有权
    制造片上电感器及相关结构的方法

    公开(公告)号：US06396122B1

    公开(公告)日：2002-05-28

    申请号：US09658483

    申请日：2000-09-08

    Applicant: David Howard ,  Bin Zhao ,  Q. Z. Liu

    Inventor： David Howard ,  Bin Zhao ,  Q. Z. Liu

    IPC: H01L2900

    CPC classification number: H01L28/10 ,  H01L27/08

    Abstract: According to various disclosed embodiments, a conductor is patterned in a dielectric. The conductor can be patterned, for example, in the shape of a square spiral. The conductor can comprise, for example, copper, aluminum, or copper-aluminum alloy. The dielectric can be, for example, silicon oxide or a low-k dielectric. A spin-on matrix containing high permeability particles is then deposited adjacent to the patterned conductor. The high permeability particles comprise material having a permeability substantially higher than the permeability of the dielectric. The high permeability particles can comprise, for example, nickel, iron, nickel-iron alloy, or magnetic oxide. As a result, an inductor having a high inductance value is achieved without lowering the quality factor of the inductor.

    Abstract translation: 根据各种公开的实施例，导体在电介质中图案化。 导体可以被图案化，例如，呈正方形螺旋形。 导体可以包括例如铜，铝或铜 - 铝合金。 电介质可以是例如氧化硅或低k电介质。 然后将包含高磁导率颗粒的旋涂基体沉积在图案化导体附近。 高磁导率颗粒包括具有比电介质的磁导率显着更高的磁导率的材料。 高磁导率颗粒可以包括例如镍，铁，镍 - 铁合金或磁性氧化物。 结果，实现了具有高电感值的电感器，而不降低电感器的品质因数。

    Method for selective fabrication of high capacitance density areas in a low dielectric constant material
    4.
    发明授权
    Method for selective fabrication of high capacitance density areas in a low dielectric constant material 有权
    用于在低介电常数材料中选择性地制造高电容密度区域的方法

    公开(公告)号：US07049246B1

    公开(公告)日：2006-05-23

    申请号：US09575055

    申请日：2000-05-19

    Applicant: Q. Z. Liu ,  David Feiler ,  Bin Zhao ,  Phil N. Sherman ,  Maureen Brongo

    Inventor： Q. Z. Liu ,  David Feiler ,  Bin Zhao ,  Phil N. Sherman ,  Maureen Brongo

    IPC: H01L21/302 ,  H01L21/461 ,  H01L21/20 ,  H01L21/8242

    CPC classification number: H01L28/86 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Method for selective fabrication of high capacitance density areas in a low dielectric constant material and related structure are disclosed. In one embodiment, a first area of a dielectric layer is covered while a second area of the dielectric layer is exposed to a dielectric conversion source. The exposure causes the dielectric constant of the dielectric layer in the second area to increase. A number of interconnect trenches are etched in the first area of the dielectric and a number of capacitor trenches are etched in the second area of the dielectric. The interconnect trenches and the capacitor trenches are then filled with an appropriate metal, such as copper, and a chemical mechanical polish is performed. The second area in which the capacitor trenches have been etched and filled has a higher capacitance density relative to the first area.

    Abstract translation: 公开了用于选择性地制造低介电常数材料和相关结构中的高电容密度区域的方法。 在一个实施例中，电介质层的第一区域被覆盖，同时介电层的第二区域暴露于电介质转换源。 曝光导致第二区域中介电层的介电常数增加。 在电介质的第一区域中蚀刻多个互连沟槽，并且在电介质的第二区域中蚀刻多个电容器沟槽。 然后用适当的金属（例如铜）填充互连沟槽和电容器沟槽，并进行化学机械抛光。 其中电容器沟槽被蚀刻和填充的第二区域相对于第一区域具有较高的电容密度。

    Fabrication of improved low-k dielectric structures
    5.
    发明授权
    Fabrication of improved low-k dielectric structures 有权
    改进的低k电介质结构的制造

    公开(公告)号：US06444136B1

    公开(公告)日：2002-09-03

    申请号：US09559292

    申请日：2000-04-25

    Applicant: Q. Z. Liu ,  Bin Zhao

    Inventor： Q. Z. Liu ,  Bin Zhao

    IPC: B44C122

    CPC classification number: H01L21/02134 ,  H01L21/02351 ,  H01L21/31058 ,  H01L21/3124 ,  H01L21/76802 ,  H01L21/76825 ,  H01L21/76831

    Abstract: Fabrication of improved low-k dielectric structures is disclosed. Low-k dielectric structures are fabricated while overcoming the otherwise existing problems associated with the use of low-k dielectric materials. In one embodiment, the physical properties of a low-k dielectric material is modified by exposing the low-k dielectric material to electron beams. The exposed portion of the low-k dielectric material becomes easier to etch and clean and exhibits greater mechanical strength and a reduction in absorption of moisture. In another embodiment, a number of incremental exposure and etch steps are performed to fabricate a desired structure. In yet another embodiment, the steps of exposure of a low-k dielectric material are combined with the etch steps. The exposure and the etching of the low-k dielectric material are performed concurrently in the same system. In still another embodiment, a single exposure and a single etch step are utilized to fabricate a desired structure. All the disclosed embodiments can be practiced by exposing the low-k dielectric material to ion beams instead of electron beams.

    Abstract translation: 公开了改进的低k电介质结构的制造。 制造低k电介质结构，同时克服与使用低k电介质材料相关的其他现有问题。 在一个实施例中，通过将低k电介质材料暴露于电子束来修改低k电介质材料的物理性质。 低k电介质材料的暴露部分变得更容易蚀刻和清洁，并且表现出更大的机械强度和减少吸湿性。 在另一个实施例中，执行多个增量曝光和蚀刻步骤以制造期望的结构。 在另一个实施例中，将低k电介质材料的曝光步骤与蚀刻步骤组合。 在同一系统中同时进行低k电介质材料的曝光和蚀刻。 在另一个实施例中，利用单次曝光和单个蚀刻步骤来制造所需的结构。 所有公开的实施例可以通过将低k电介质材料暴露于离子束而不是电子束来实施。

    On-chip inductors
    6.
    发明授权
    On-chip inductors 有权
    片上电感

    公开(公告)号：US07173318B2

    公开(公告)日：2007-02-06

    申请号：US09754806

    申请日：2001-01-02

    Applicant: Q Z Liu ,  Bin Zhao ,  David Howard

    Inventor： Q Z Liu ,  Bin Zhao ,  David Howard

    IPC: H01L29/00

    CPC classification number: H01L28/10 ,  H01L27/08

    Abstract: Method for fabrication of on-chip inductors and related structure are disclosed. According to one embodiment, inductors are formed by patterning conductors within a certain dielectric layer in a semiconductor die. Thereafter, the entire dielectric layer in the semiconductor die is subjected to a blanket implantation or sputtering of high permeability material. According to another embodiment, a first area in a semiconductor die is covered, for example, with photoresist. A second area in the semiconductor die includes a patterned conductor which is to be used as an inductor. The patterned conductor is also covered, for example, with photoresist. The second area, excluding the covered patterned conductor, is subjected to implantation or sputtering of high permeability material. According to yet another embodiment, a first area of a semiconductor die is covered, for example, with photoresist. A second area in the semiconductor area includes a patterned conductor which is to be used as an inductor. This second area, including the patterned conductor, is subjected to implantation or sputtering of high permeability material. The implantation or sputtering of high permeability materials result in the inductors having much higher inductance values than they would otherwise have.

    Abstract translation: 公开了片上电感器的制造方法和相关结构。 根据一个实施例，电感器通过在半导体管芯内的某个介电层内图案化导体而形成。 此后，对半导体管芯中的整个电介质层进行高导磁率材料的覆盖注入或溅射。 根据另一实施例，半导体管芯中的第一区域例如被光致抗蚀剂覆盖。 半导体管芯中的第二区域包括用作电感器的图案化导体。 图案化的导体也例如用光致抗蚀剂覆盖。 除了被覆盖的图案导体之外的第二区域经受高磁导率材料的注入或溅射。 根据另一个实施例，半导体管芯的第一区域例如被光致抗蚀剂覆盖。 半导体区域中的第二区域包括用作电感器的图案化导体。 包括图案化导体的该第二区域经受高磁导率材料的注入或溅射。 高磁导率材料的注入或溅射导致电感器的电感值高于原来的电感值。

    Pulse width modulation with effective high duty resolution
    9.
    发明授权
    Pulse width modulation with effective high duty resolution 有权
    具有高占空比分辨率的脉宽调制

    公开(公告)号：US09490792B2

    公开(公告)日：2016-11-08

    申请号：US12703239

    申请日：2010-02-10

    Applicant: Bin Zhao

    Inventor： Bin Zhao

    IPC: H03K7/08 ,  H04N9/31 ,  H05B33/08 ,  H02M1/084

    CPC classification number: H03K7/08 ,  H02M1/084 ,  H04N9/3123 ,  H05B33/0818 ,  H05B33/0845 ,  Y02B20/346

    Abstract: A pulse width modulation (PWM) signal generator generates a PWM signal having a specified effective PWM duty resolution for a corresponding cycle window. The PWM signal generator receives an N-bit value representing a duty to be implemented and sets values X and Y to the M least significant bits and the N-M most significant bits, respectively, of the N-bit value. The value M can be determined based on the value N and a maximum implementable frequency of a clock signal used to time the generation of each PWM cycle. The PWM signal generator generates a cycle window of 2M PWM cycles, each PWM cycle of the cycle window having a duty of either Y or Y+1. The number of PWM cycles in the cycle window having the duty Y+1 is based on the value X and the PWM cycles having a particular duty are contiguous within the cycle window.

    Abstract translation: 脉冲宽度调制（PWM）信号发生器产生对于相应的周期窗口具有指定的有效PWM占空比分辨率的PWM信号。 PWM信号发生器接收表示要实现的占空比的N位值，并将值X和Y分别设置为N位值的M个最低有效位和N-M个最高有效位。 可以基于用于时间产生每个PWM周期的时钟信号的值N和最大可实施频率来确定值M. PWM信号发生器产生2M个PWM周期的周期窗口，周期窗口的每个PWM周期具有Y或Y + 1的占空比。 具有占空比Y + 1的周期窗口中的PWM周期的数量基于值X，并且具有特定占空比的PWM周期在周期窗口内是连续的。

    SYSTEMS AND METHODS FOR VISUALIZING A CALL OVER NETWORK WITH A CALLER READINESS DIALOG BOX
    10.
    发明申请
    SYSTEMS AND METHODS FOR VISUALIZING A CALL OVER NETWORK WITH A CALLER READINESS DIALOG BOX 有权
    使用电话簿无线对话框可视化网络呼叫的系统和方法

    公开(公告)号：US20150381816A1

    公开(公告)日：2015-12-31

    申请号：US14500968

    申请日：2014-09-29

    Applicant: Bin Zhao ,  Jonathan Li

    Inventor： Bin Zhao ,  Jonathan Li

    IPC: H04M3/56 ,  H04M3/432

    CPC classification number: H04L43/0864 ,  H04L12/18 ,  H04L12/1827 ,  H04L12/1831 ,  H04L41/5038 ,  H04L43/045 ,  H04L43/062 ,  H04L43/0852 ,  H04L43/10 ,  H04L43/50 ,  H04L45/123 ,  H04L47/283 ,  H04L47/722 ,  H04L51/34 ,  H04L65/1066 ,  H04L65/4038 ,  H04M1/2535 ,  H04M1/72547 ,  H04M3/2236 ,  H04M3/432 ,  H04M3/563 ,  H04M3/565 ,  H04M7/0084 ,  H04M2250/62 ,  H04M2250/74 ,  H04W4/16

    Abstract: Systems and methods for a readiness dialog box for a call over network (CON) are provided. In some embodiments, the readiness dialog box is presented to the callers prior to the onset of the call. It presents the other participant's and their status. For example, it may indicate which participants are online, but not yet ready, those who are ready, and those not available. It also enables the caller to send messages (both preconfigured and customized) to the other participants. Once sufficient participants have joined, the call may start. Sufficiency of participants could include a quorum of individuals, may require that specific participants are ready, everyone is ready, or may be time dependent. The participant requirements may be configured by the individual setting up the call based upon call type.

    Abstract translation: 提供了一种用于网络呼叫（CON）的准备对话框的系统和方法。 在一些实施例中，准备对话框在呼叫开始之前呈现给呼叫者。 它提供了另一个参与者及其状态。 例如，它可以指示哪些参与者在线，但尚未准备好，准备好的人以及不可用的参与者。 它还使呼叫者能够向其他参与者发送消息（预配置和自定义）。 一旦有足够的参与者加入，呼叫可能开始。 参与者的充分性可能包括个人的法定人数，可能要求具体参与者准备好，每个人都准备好了，或者可能是时间依赖的。 参与者要求可以由个人根据呼叫类型设置呼叫进行配置。

Patent Agency Ranking