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    HIERARCHICAL POWER ESTIMATION AND THROTTLING IN A PROCESSOR-BASED SYSTEM IN AN INTEGRATED CIRCUIT (IC) CHIP
    1.
    发明申请
    HIERARCHICAL POWER ESTIMATION AND THROTTLING IN A PROCESSOR-BASED SYSTEM IN AN INTEGRATED CIRCUIT (IC) CHIP 有权

    公开(公告)号：US20240427411A1

    公开(公告)日：2024-12-26

    申请号：US18626645

    申请日：2024-04-04

    Applicant: QUALCOMM Incorporated

    Inventor： Vinod Chamarty ,  Sagar Koorapati ,  Alon Naveh

    IPC: G06F1/3293

    Abstract: Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip, and related power management and power throttling methods are disclosed. The IC chip includes a processor as well as integrated supporting processing devices for the processor. The hierarchical power management system controls power consumption of devices in the IC chip to achieve the desired performance in the processor-based system based on activity power events generated from local activity monitoring of devices in the IC chip. To mitigate the delay in the reporting of activity power event of a monitored processing device that may affect throttling of power consumption for the IC chip, the power consumption of a monitored processing device can also be throttled locally throttle its power consumption. This gives reaction time for the power management system to receive and process activity power events to throttle power consumption in the IC chip.

    INTEGRATED CIRCUITS (IC) CHIPS INCLUDING THROTTLE REQUEST ACCUMULATE CIRCUITS FOR CONTROLLING POWER CONSUMED IN PROCESSING CIRCUITS AND RELATED METHODS
    2.
    发明申请
    INTEGRATED CIRCUITS (IC) CHIPS INCLUDING THROTTLE REQUEST ACCUMULATE CIRCUITS FOR CONTROLLING POWER CONSUMED IN PROCESSING CIRCUITS AND RELATED METHODS 有权

    公开(公告)号：US20240427400A1

    公开(公告)日：2024-12-26

    申请号：US18623217

    申请日：2024-04-01

    Applicant: QUALCOMM Incorporated

    Inventor： Sagar Koorapati ,  Vinod Chamarty ,  Gaurav Sanjeev Kirtane ,  Pushkin Raj Pari ,  Nitin Makhija ,  Alon Naveh

    IPC: G06F1/28

    Abstract: The processor-based system includes a throttle request accumulate circuit to receive throttle requests, determine a highest or most aggressive throttle value among the throttle requests, and generate a throttle control signal configured to throttle activity in the plurality of processing circuits. Throttle requests have throttle values corresponding to a reduction in activity in at least a portion of the plurality of processing circuits and may correspond to a particular number of cycles of reduced activity in a window of cycles. In addition to reducing response time to local events or conditions compared to waiting for a hierarchical response, the throttle request accumulate circuit accumulates throttle requests from all circuits that adjust or throttle activity in the plurality of processing circuits, and ensures that the net effective throttle controlling activity in the processing circuits at any given time is based on the highest throttle value of those accumulated throttle requests.

    BROADCASTING POWER LIMITING MANAGEMENT RESPONSES IN A PROCESSOR-BASED SYSTEM IN AN INTEGRATED CIRCUIT (IC) CHIP
    4.
    发明申请
    BROADCASTING POWER LIMITING MANAGEMENT RESPONSES IN A PROCESSOR-BASED SYSTEM IN AN INTEGRATED CIRCUIT (IC) CHIP 有权

    公开(公告)号：US20240428024A1

    公开(公告)日：2024-12-26

    申请号：US18339504

    申请日：2023-06-22

    Applicant: QUALCOMM Incorporated

    Inventor： Sagar Koorapati ,  Vinod Chamarty ,  Alon Naveh

    IPC: G06K7/10

    Abstract: Broadcasting power limiting management responses in a processor-based system in an integrated circuit (IC) chip is disclosed herein. In one aspect, an IC chip comprises a processor-based system that includes a power estimation and limiting (PEL) circuit, a Limit Management Throughput Throttle (LMTT) source circuit, a plurality of activity management (AM) circuits, and an LMTT bus communicatively coupling the LMTT source circuit with each AM circuit of the plurality of AM circuits. The LMTT source circuit receives a power limiting management response from a PEL circuit via a communications network of the processor-based system, and generates an LMTT command based on the power limiting management response. The LMTT source circuit broadcasts the LMTT command to each AM circuit of the plurality of AM circuits via the LMTT bus.

    TIME SYNCHRONIZATION OF COLLECTING AND REPORTING POWER EVENTS BETWEEN HIERARCHICAL POWER THROTTLING CIRCUITS IN A HIERARCHICAL POWER MANAGEMENT SYSTEM
    5.
    发明申请
    TIME SYNCHRONIZATION OF COLLECTING AND REPORTING POWER EVENTS BETWEEN HIERARCHICAL POWER THROTTLING CIRCUITS IN A HIERARCHICAL POWER MANAGEMENT SYSTEM 有权

    公开(公告)号：US20240427393A1

    公开(公告)日：2024-12-26

    申请号：US18626683

    申请日：2024-04-04

    Applicant: QUALCOMM Incorporated

    Inventor： Vinod Chamarty ,  Sagar Koorapati ,  Sreeram Jayadev ,  Alon Naveh

    IPC: G06F1/26

    Abstract: Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip, and related power management and power throttling methods are disclosed. The IC chip includes a processor as well as integrated supporting processing devices for the processor. The hierarchical power management system controls power consumption of devices in the IC chip to achieve the desired performance in the processor-based system based on activity power events generated from local activity monitoring of devices in the IC chip. The circuit levels in the hierarchical power management systems are configured to be time synchronized with each other for the synchronized monitoring and reporting of activity samples and activity power events, and the generation of power limiting management responses to throttle power consumption in the IC chip.

    TIME SYNCHRONIZATION OF COLLECTING AND REPORTING POWER EVENTS BETWEEN HIERARCHICAL POWER THROTTLING CIRCUITS IN A HIERARCHICAL POWER MANAGEMENT SYSTEM
    6.
    发明申请
    TIME SYNCHRONIZATION OF COLLECTING AND REPORTING POWER EVENTS BETWEEN HIERARCHICAL POWER THROTTLING CIRCUITS IN A HIERARCHICAL POWER MANAGEMENT SYSTEM 有权

    公开(公告)号：US20240427392A1

    公开(公告)日：2024-12-26

    申请号：US18339430

    申请日：2023-06-22

    Applicant: QUALCOMM Incorporated

    Inventor： Vinod Chamarty ,  Sagar Koorapati ,  Sreeram Jayadev ,  Alon Naveh

    IPC: G06F1/26

    Abstract: Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip, and related power management and power throttling methods are disclosed. The IC chip includes a processor as well as integrated supporting processing devices for the processor. The hierarchical power management system controls power consumption of devices in the IC chip to achieve the desired performance in the processor-based system based on activity power events generated from local activity monitoring of devices in the IC chip. The circuit levels in the hierarchical power management systems are configured to be time synchronized with each other for the synchronized monitoring and reporting of activity samples and activity power events, and the generation of power limiting management responses to throttle power consumption in the IC chip.

    Method and Apparatus For Flexible Cache Partitioning By Sets And Ways Into Component Caches
    9.
    发明申请
    Method and Apparatus For Flexible Cache Partitioning By Sets And Ways Into Component Caches 有权
    用于灵活高速缓存分组的方法和装置通过集合和方式进入组件高速缓存

    公开(公告)号：US20160019157A1

    公开(公告)日：2016-01-21

    申请号：US14333981

    申请日：2014-07-17

    Applicant: QUALCOMM Incorporated

    Inventor： Subbarao Palacharla ,  Moinul Khan ,  Alain Artieri ,  Kedar Bhole ,  Vinod Chamarty ,  Pankaj Chaurasia ,  Raghu Sankuratri

    IPC: G06F12/08 ,  G06F12/10 ,  G06F12/12

    CPC classification number: G06F12/0893 ,  G06F12/084 ,  G06F12/0895 ,  G06F12/10 ,  G06F12/12 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/601 ,  G06F2212/6046 ,  Y02D10/13

    Abstract: Aspects include computing devices, systems, and methods for partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests specifying component cache identifiers, and match the component cache identifiers with records correlating traits of the component cache identifiers with in a component cache configuration table. The component cache traits may include a set shift trait, set offset trait, and target ways, which may define the locations of the component caches in the system cache. The system cache memory controller may also receive a physical address for the system cache in the system cache access request, determine an indexing mode for the component cache, and translate the physical address for the component cache.

    Abstract translation: 方面包括计算设备，系统和用于通过集合和方式将系统高速缓存分组到组件高速缓存中的方法。 系统高速缓冲存储器控制器可以管理组件高速缓存并管理对组件高速缓存的访问。 系统高速缓冲存储器控制器可以接收指定组件高速缓存标识符的系统高速缓存访​​问请求，并且将组件高速缓存标识符与组件高速缓存标识符的特征与组件高速缓存配置表相关联的记录进行匹配。 组件缓存特征可以包括设置的移动特征，设置偏移特征和目标方式，其可以定义系统高速缓存中的组件高速缓存的位置。 系统高速缓冲存储器控制器还可以在系统高速缓存访​​问请求中接收系统高速缓存的物理地址，确定组件高速缓存的索引模式，并转换组件高速缓存的物理地址。

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