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1.发明授权MOSFET predrive circuit with independent control of the output voltage rise and fall time, with improved latch immunity 失效MOSFET预驱动电路具有独立的输出电压上升和下降时间控制，具有提高的锁存抗扰度公开(公告)号：US06268755B1
公开(公告)日：2001-07-31
申请号：US08963836
申请日：1997-11-04
IPC分类号： H03K190185
CPC分类号： H03K19/018585 , H03K19/00361
摘要： A voltage level shifting circuit (60) and method for accomplishing a voltage level change includes a voltage level shifting circuit (65) to change an input voltage to a shifted voltage level. A second stage (67) is connected between a voltage source at the shifted voltage level (68) and the reference potential. The second stage (67) includes active devices (66,82) that are controlled by the voltage level shifting circuit (65). The second stage (67) also includes slope resistors (86,88) connected in series between the active devices (66,82) of the second stage (67).
摘要翻译： 电压电平移动电路（60）和用于实现电压电平变化的方法包括将输入电压改变到移位的电压电平的电压电平移位电路（65）。 第二级（67）连接在变换的电压电平（68）的电压源和参考电位之间。 第二级（67）包括由电压电平移位电路（65）控制的有源器件（66,82）。 第二级（67）还包括串联连接在第二级（67）的有源器件（66,82）之间的斜率电阻器（86,88）。
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公开(公告)号：US06236098B1
公开(公告)日：2001-05-22
申请号：US09061452
申请日：1998-04-16
IPC分类号： H01L31058
CPC分类号： H01L23/34 , H01L2224/05001 , H01L2224/05022 , H01L2224/05023 , H01L2224/05027 , H01L2224/05567 , H01L2224/05572 , H01L2224/13 , H01L2924/3011
摘要： An integrated circuit chip (10, 50, 100) may comprise an integrated circuit (14, 54, 108, 110, 112) formed in a semiconductor layer (12, 52, 102). A thermal contact (16, 56, 116) may be formed at a high temperature region of the integrated circuit (14, 54, 108, 110, 112). A thick plated metal layer (40, 80, 140) may be generally isolated from the integrated circuit (14, 54, 108, 110, 112). The thick plated metal layer (40, 80, 140) may include a base (42, 82, 142) and an exposed surface (44, 84, 144) opposite the base (42, 82, 142). The base (42, 82, 142) may be coupled to the thermal contact (16, 56, 116) to receive thermal energy of the high temperature region. The exposed surface (44, 84, 144) may dissipate thermal energy received by the thick plated metal layer (40, 80, 140).
摘要翻译： 集成电路芯片（10,50,100）可以包括形成在半导体层（12,52,102）中的集成电路（14,54,108,110,112）。 可以在集成电路（14,54,108,110,112）的高温区域形成热接触（16,56,116）。 厚电镀金属层（40,80,140）可以通常与集成电路（14,54,108,110,112）隔离。 厚电镀金属层（40,80,140）可以包括基部（42,82,142）和与基部（42,82,142）相对的暴露表面（44,84,144）。 基座（42,82,142）可以联接到热接触件（16,56,116）以接收高温区域的热能。 暴露表面（44,84,144）可以消散由厚镀金属层（40,80,140）接收的热能。
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公开(公告)号：US06373094B1
公开(公告)日：2002-04-16
申请号：US09908024
申请日：2001-07-18
IPC分类号： H01L29788
摘要： An EEPROM cell (10) formed on a substrate (18) using conventional process steps is provided. The cell (10) includes first (12) and second (14) conductive regions in the substrate (18) below the substrate's outer surface (28), and the first (12) and second (14) conductive regions are laterally displaced from one another by a predetermined distance (32). The cell (10) also includes an insulating layer (20) outwardly from the outer surface (28) of the substrate (18) positioned so that its edges are substantially in alignment between the first (12) and second (14) conductive regions. The cell (10) further includes a floating gate layer (22) outwardly from the insulating layer (20) and in substantially the same shape as the insulating layer (20). The cell (10) also includes a diffusion region (24 or 26) that extends laterally from at least one of the first (12) and second (14) conductive regions so as to overlap with the insulating layer (20). The diffusion region (24 or 26) provides a source of charge for placement on the floating gate layer (22) when programming the EEPROM cell (10).
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公开(公告)号：US5812006A
公开(公告)日：1998-09-22
申请号：US739375
申请日：1996-10-29
申请人： Ross E. Teggatz , Joseph A. Devore , Kenneth G. Buss , Thomas A. Schmidt , Taylor R. Efland , Stephen C. Kwan
发明人： Ross E. Teggatz , Joseph A. Devore , Kenneth G. Buss , Thomas A. Schmidt , Taylor R. Efland , Stephen C. Kwan
IPC分类号： H03K17/06 , H03K17/082 , H03K5/08
CPC分类号： H03K17/063 , H03K17/0822
摘要： An optimized power output clamping structure, includes a power output transistor having a first breakdown voltage and a breakdown structure having a second breakdown voltage coupled to the power output transistor. The second breakdown voltage is less than the first breakdown voltage and follows the first breakdown voltage across all temperature and semiconductor process variations. This feature allows a reduction in breakdown voltage guardbanding and increases output structure reliability. A method of protecting a circuit from inductive flyback is also disclosed. The method includes the steps of driving an inductive load with drive circuitry, turning off the inductive load, and clamping an inductive voltage at a voltage magnitude that protects the drive circuitry from breakdown across all temperature and processing variations.
摘要翻译： 优化的功率输出钳位结构包括具有第一击穿电压的功率输出晶体管和具有耦合到功率输出晶体管的第二击穿电压的击穿结构。 第二击穿电压小于第一击穿电压，并且遵循所有温度和半导体工艺变化的第一击穿电压。 该特征允许降低击穿电压保护带并增加输出结构的可靠性。 还公开了一种保护电路免受感应回扫的方法。 该方法包括以下步骤：利用驱动电路驱动感性负载，关闭感性负载，以及钳位感应电压，电压幅度保护驱动电路不受所有温度和处理变化的影响。
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公开(公告)号：US5675241A
公开(公告)日：1997-10-07
申请号：US672125
申请日：1996-06-27
CPC分类号： G05F3/247
摘要： A circuit and method for providing a low drop out voltage regulator. A source follower circuit is provided having a transistor (MD1) with an output terminal for driving a load at its source terminal and a voltage supply coupled to the drain terminal. At least one diode (D1) is coupled between the gate terminal and a ground reference to provide a predetermined voltage at the gate of the transistor (MD1). A voltage multiplier circuit is provided having an input (IN) for receiving an oscillating input voltage and a charge storage device (39) coupled between the oscillating input and a voltage reference (Vref), and being further coupled in series with the voltage reference and then to the gate terminal of the transistor (MD1). The oscillating input voltage is used to charge the charge storage device (39) to a voltage approximately equal to the voltage reference. When the supply voltage falls below the normal level, the series combination of the voltage reference and the charge storage device provides a multiplied voltage at the gate of the transistor, for example a voltage of twice the reference voltage. This high gate voltage keeps the output at the source of the transistor at a high voltage that is approximately equal to the supply voltage, such that the circuit provides a low drop out voltage under low supply voltage conditions.
摘要翻译： 一种用于提供低压降稳压器的电路和方法。 源极跟随器电路具有晶体管（MD1），其具有用于驱动其源极端子处的负载的输出端子和耦合到漏极端子的电压源。 至少一个二极管（D1）耦合在栅极端子和接地基准之间，以在晶体管（MD1）的栅极处提供预定的电压。 提供了具有用于接收振荡输入电压的输入（IN）和耦合在振荡输入和电压参考（Vref）之间的电荷存储装置（39）的电压倍增器电路，并进一步与电压基准串联耦合， 然后到晶体管（MD1）的栅极端子。 振荡输入电压用于将电荷存储装置（39）充电至大致等于电压基准的电压。 当电源电压低于正常电平时，电压基准和电荷存储装置的串联组合在晶体管的栅极处提供倍增电压，例如两倍于参考电压的电压。 该高栅极电压将晶体管源极处的输出保持在大致等于电源电压的高电压，使得该电路在低电源电压条件下提供低压降电压。
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6.发明授权MOS ESD CDM clamp with integral substrate injection guardring and method for fabrication 有权具有集成衬底注入防护罩的MOS ESD CDM夹具及其制造方法公开(公告)号：US06940131B2
公开(公告)日：2005-09-06
申请号：US10609920
申请日：2003-06-30
IPC分类号： H01L27/02 , H01L29/06 , H01L29/423 , H01L23/62
CPC分类号： H01L29/0692 , H01L27/0266 , H01L29/4238
摘要： The present invention includes a MOS device (100) that has a P-type substrate (102) and an N-type drain region (104) formed within the substrate (102). An annular N-type source region (106) generally surrounds the drain region (104). The source region (106) serves as both the source for the MOS device (100) and a sacrificial collector guard ring for an electrostatic discharge protection circuit. An annular gate region (110) generally surrounds the drain region (104) and is electrically insulated from the drain region (104) and electrically connected to the source region (106). An annular P-type bulk region (108) generally surrounds the source region (106) and is electrically connected to the source region (106).
摘要翻译： 本发明包括具有形成在基板（102）内的P型基板（102）和N型漏极区（104）的MOS器件（100）。 环形N型源极区域（106）通常围绕漏极区域（104）。 源极区域（106）用作MOS器件（100）的源极和用于静电放电保护电路的牺牲集电极保护环。 环形栅极区域（110）通常围绕漏极区域（104）并且与漏极区域（104）电绝缘并且电连接到源极区域（106）。 环形P型体区域（108）通常围绕源极区域（106）并且电连接到源极区域（106）。
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公开(公告)号：US6111737A
公开(公告)日：2000-08-29
申请号：US267490
申请日：1999-03-11
CPC分类号： H01L27/0251
摘要： An internal circuitry protection scheme which protects on-IC circuitry when an external regulator voltage pin is shorted to a higher voltage. The circuit prevents damage to the on-die circuitry that is on the internal voltage rail, by clamping the received voltage, thereby eliminating the chance of damaging the on die circuitry. The circuit offers protection even if the voltage difference is large, but the difference remains small between the internal rail and the external regulated voltage under normal operation.
摘要翻译： 内部电路保护方案，当外部稳压器电压引脚短路到较高电压时，保护IC内部电路。 该电路通过钳位接收到的电压来防止损坏内部电压轨上的片上电路，从而消除了损坏管芯电路的可能性。 即使电压差大，电路也能提供保护，但在正常工作状态下，内部轨道与外部调节电压之间的差异仍然很小。
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公开(公告)号：US5710515A
公开(公告)日：1998-01-20
申请号：US480063
申请日：1995-06-07
IPC分类号： G01K7/01 , G01R31/28 , G01R31/30 , G01R31/3167 , H01L23/34 , G01R31/02 , G01R31/00 , G08B21/00
CPC分类号： H01L23/34 , G01K7/01 , G01R31/30 , G01R31/3167 , H01L2924/0002
摘要： A testable temperature warning circuit (120) in an integrated circuit substrate (124) provides a warning if the substrate temperature exceeds a critical temperature. A programming circuit (140) controls a selection, circuit (128) to establish a programmably selectable temperature at either the critical temperature or a second predetermined temperature lower than the critical temperature to enable the warning circuit operation to be tested at a temperature lower than the critical temperature. In one embodiment, the selection circuit 128 comprises a current source that produces a voltage drop across the resistor 121 and base-emitter of the transistor 122 produces a substrate temperature indicating current of magnitude related to the temperature of the substrate. The substrate temperature indicating current at the second temperature is extrapolatingly related to the substrate temperature indicating current at the critical temperature. A method is also presented for testing a temperature warning circuit fabricated in an integrated circuit substrate.
摘要翻译： 如果衬底温度超过临界温度，则集成电路衬底（124）中的可测温度警告电路（120）提供警告。 编程电路（140）控制选择电路（128）在临界温度或低于临界温度的第二预定温度下建立可编程选择的温度，以使报警电路操作能够在低于 临界温度。 在一个实施例中，选择电路128包括在电阻器121上产生电压降的电流源，并且晶体管122的基极 - 发射极产生指示与衬底温度相关的电流幅度的衬底温度。 指示在第二温度下的电流的衬底温度与指示临界温度下的电流的衬底温度外推相关。 还提出了一种用于测试在集成电路基板中制造的温度警告电路的方法。
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公开(公告)号：US06324044B1
公开(公告)日：2001-11-27
申请号：US09305571
申请日：1999-05-05
IPC分类号： H02H100
CPC分类号： G06F13/385
摘要： A controlled area network (CAN) driver provides improved symmetry between its differential output signals CAN-H and CAN-L, and provides protection for its low voltage devices from voltage transients occurring on its output lines. A plurality of CAN drivers 80 are serially interconnected to form a driver system, wherein each downstream driver stage receives a time-delayed form of the digital input signal TxD, each stage providing a time-delayed contribution to the differential output signals of the overall driver system.
摘要翻译： 控制区域网络（CAN）驱动器在其差分输出信号CAN-H和CAN-L之间提供改进的对称性，并为其低压器件提供对其输出线路上发生的电压瞬变的保护。 多个CAN驱动器80串联互连以形成驱动器系统，其中每个下游驱动器级接收时间延迟形式的数字输入信号TxD，每个级为整个驱动器的差分输出信号提供时间延迟的贡献 系统。
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10.发明授权Method for current ballasting and busing over active device area using a multi-level conductor process 失效使用多层导体工艺在有源器件区域上进行电流镇流和放电的方法
公开(公告)号：US5801091A
公开(公告)日：1998-09-01
申请号：US903970
申请日：1997-07-31
申请人： Taylor R. Efland , Satwinder Malhi , Michael C. Smayling , Joseph A. Devore , Ross E. Teggatz , Alec J. Morton
发明人： Taylor R. Efland , Satwinder Malhi , Michael C. Smayling , Joseph A. Devore , Ross E. Teggatz , Alec J. Morton
IPC分类号： H01L23/482 , H01L23/528 , H01L29/417 , H01L29/78 , H01L21/44
CPC分类号： H01L23/5286 , H01L23/4824 , H01L29/41725 , H01L29/41758 , H01L29/7816 , H01L29/7835 , H01L2924/0002
摘要： The device has a semiconductor chip having active circuitry in the face thereof. The circuitry has busing over it containing two conductive layers having a plurality of contacts and vias with spacings between them that alternate with respect to one another to provide current ballasting and improved switching uniformity. The spacings between the alternating contacts and vias provide regions of maximum conductor thickness and therefore reduces the busing resistance. Staggering the rows of alternating contacts and vias provides further current ballasting. A first conducting layer is used to contact and provide electrically isolated low resistive conducting paths to the various semiconductor regions while the second conducting region is used to provide selective contact to the first conductive layer, thus providing a means of busing large currents over active semiconductor area without sacrificing performance parameters.
摘要翻译： 该器件具有在其表面上具有有源电路的半导体芯片。 该电路具有引线，其中包含两个具有多个触点的导电层和在它们之间具有相互间交替的间隙的通孔，以提供电流镇流和改善的开关均匀性。 交替触点和通孔之间的间距提供最大导体厚度的区域，因此降低了阻抗。 交错的交替触点和通孔的排列提供了进一步的电流镇流。 第一导电层用于接触并提供到各种半导体区域的电隔离的低电阻导电路径，而第二导电区域用于提供与第一导电层的选择性接触，从而提供在有源半导体区域上引入大电流的装置 而不牺牲性能参数。
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