公开(公告)号：US20220149058A1

公开(公告)日：2022-05-12

申请号：US17502798

申请日：2021-10-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiyuki KAWASHIMA

IPC: H01L27/11521 ,  G11C11/54 ,  H01L29/423 ,  G11C11/56

Abstract: A plurality of non-volatile memory cells are used to realize synapses in a neural network circuit. A semiconductor device includes a memory cell array in which a plurality of non-volatile memory cells are arranged in an array. Each of the plurality of non-volatile memory cells has: a control gate electrode and a memory gate electrode that extend in a Y direction; a drain region; and a source region. Each of the plurality of drain regions is electrically connected to a bit line extending in a Y direction, and each of the plurality of source regions is electrically connected to a source line extending in an X direction.

公开(公告)号：US20180061997A1

公开(公告)日：2018-03-01

申请号：US15626092

申请日：2017-06-17

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki KAWASHIMA ,  Masao INOUE ,  Atsushi YOSHITOMI

IPC: H01L29/792 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/785

Abstract: A memory cell includes a control gate electrode and a memory gate electrode. The control gate electrode is formed over the upper surface and the sidewall of a fin FA including apart of a semiconductor substrate. The memory gate electrode is formed over one side surface of the control gate electrode and the upper surface and the sidewall of the fin through an ONO film, in a position adjacent to the one side surface of the control gate electrode. Further, the control gate electrode and the memory gate electrode are formed of n-type polycrystalline silicon. A first metal film is provided between the gate electrode and the control gate electrode. A second metal film is provided between the ONO film and the memory gate electrode. A work function of the first metal film is greater than a work function of the second metal film.

公开(公告)号：US20150171160A1

公开(公告)日：2015-06-18

申请号：US14636311

申请日：2015-03-03

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki KAWASHIMA ,  Koichi TOBA ,  Yasushi ISHII ,  Toshikazu MATSUI ,  Takashi HASHIMOTO

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/60 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/105 ,  H01L27/10805 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11573 ,  H01L28/40

Abstract: In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.

公开(公告)号：US20220148662A1

公开(公告)日：2022-05-12

申请号：US17502832

申请日：2021-10-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiyuki KAWASHIMA

IPC: G11C16/28 ,  G11C11/54 ,  G11C16/04 ,  H01L29/423 ,  H01L29/792 ,  G11C16/10 ,  G11C16/16 ,  G06N3/063

Abstract: In a case of achievement of a neural network circuit using a plurality of nonvolatile memory cells, a technique capable of accurately reading information recorded in the plurality of nonvolatile memory cells is provided. A semiconductor device includes: a plurality of nonvolatile memory cells; a plurality of reference-current cells; and a sense amplifier comparing an electric current flowing in each of the plurality of nonvolatile memory cells and an electric current flowing in each of the plurality of reference-current cells. In this case, each cross-sectional structure of the plurality of reference-current cells is the same as each cross-sectional structure of the plurality of nonvolatile memory cells. The writing operation or the erasing operation is also performed to each of the plurality of reference-current memory cells when the writing operation or the erasing operation is performed to each of the plurality of nonvolatile memory cells.

公开(公告)号：US20200027996A1

公开(公告)日：2020-01-23

申请号：US16452261

申请日：2019-06-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masao INOUE ,  Masaru KADOSHIMA ,  Yoshiyuki KAWASHIMA ,  Ichiro YAMAKAWA

IPC: H01L29/792 ,  H01L29/423 ,  H01L29/51 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66

Abstract: A memory cell, which is a nonvolatile memory cell, includes a gate dielectric film having charge storage layer capable of holding charges, and a memory gate electrode formed on the gate dielectric film. The charge storage layer includes an insulating film containing hafnium, silicon, and oxygen, an insertion layer formed on the insulating film and containing aluminum, and an insulating film formed on the insertion layer and containing hafnium, silicon, and oxygen.

公开(公告)号：US20180366475A1

公开(公告)日：2018-12-20

申请号：US16110555

申请日：2018-08-23

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki KAWASHIMA ,  Takashi HASHIMOTO

IPC: H01L27/1157 ,  H01L29/66 ,  H01L29/423 ,  H01L29/792 ,  H01L23/528 ,  H01L29/78 ,  H01L21/02

Abstract: A semiconductor device in which the cell size is small and disturbance in reading operation is suppressed, and a method for manufacturing the semiconductor device. A first memory cell has a first memory transistor. A second memory cell has a second memory transistor. A control gate is shared by the first memory cell and the second memory cell. In plan view, the control gate is sandwiched between a first memory gate of the first memory transistor and a second memory gate of the second memory transistor.

公开(公告)号：US20180315702A1

公开(公告)日：2018-11-01

申请号：US15904346

申请日：2018-02-24

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki KAWASHIMA ,  Takashi HASHIMOTO

IPC: H01L23/522 ,  H01L27/11517 ,  H01L49/02 ,  H01L23/532 ,  H01L21/762 ,  H01L21/768

CPC classification number: H01L29/94 ,  H01L27/0629 ,  H01L27/0805 ,  H01L28/40

Abstract: This invention is to improve a performance of a semiconductor device. The semiconductor device includes a semiconductor substrate, a p-type well region formed in the semiconductor substrate, a first insulating layer formed over the p-type well region, a semiconductor layer formed over the first insulating layer, a second insulating layer formed over the semiconductor layer, and a conductor layer formed over the second insulating layer. A first capacitive element is comprised of the semiconductor layer, the second insulating layer, and the conductor layer, while a second capacitive element is comprised of the p-type well region, the first insulating layer, and the semiconductor layer, in which each of the semiconductor substrate and the semiconductor layer includes a single crystal silicon layer.

公开(公告)号：US20180053658A1

公开(公告)日：2018-02-22

申请号：US15796621

申请日：2017-10-27

Applicant: Renesas Electronics Corporation

Inventor： Kentaro SAITO ,  Hideki SUGIYAMA ,  Hiraku CHAKIHARA ,  Yoshiyuki KAWASHIMA

IPC: H01L21/28 ,  H01L29/792 ,  H01L29/66 ,  H01L27/06 ,  H01L49/02

CPC classification number: H01L21/28282 ,  H01L27/0629 ,  H01L27/11573 ,  H01L28/60 ,  H01L29/66833 ,  H01L29/792

Abstract: In a semiconductor device, a memory cell is formed of a control gate electrode and a memory gate electrode adjacent to each other, a gate insulating film formed below the control gate electrode and an insulating film formed below the memory gate electrode and having a charge accumulating part therein. Also, in this semiconductor device, a capacitive element is formed of a lower electrode, an upper electrode and a capacitive insulating film formed between the upper electrode and the lower electrode. A thickness of the lower electrode is smaller than a thickness of the control gate electrode.

公开(公告)号：US20160172201A1

公开(公告)日：2016-06-16

申请号：US15050060

申请日：2016-02-22

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki KAWASHIMA ,  Kentaro SAITO ,  Hiraku CHAKIHARA

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/66 ,  H01L29/40 ,  H01L27/115 ,  H01L29/423

CPC classification number: H01L29/40117 ,  H01L21/02164 ,  H01L21/0217 ,  H01L27/11563 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/401 ,  H01L29/42344 ,  H01L29/66833

Abstract: The present invention improves the performance of a semiconductor device. In a manufacturing method of a semiconductor device, sacrificial oxide films are formed over the side surface of a control gate electrode formed in a memory cell region, the surface of a cap insulating film formed in the memory cell region, and the surface of the part, which remains in a peripheral circuit region, of an insulating film. The step of forming the sacrificial oxide films includes the steps of: oxidizing the side surface of the control gate electrode by a thermal oxidation method; and oxidizing the surface of the cap insulating film and the surface of the part, which remains in the peripheral circuit region, of the insulating film by an ISSG oxidation method.

公开(公告)号：US20240136419A1

公开(公告)日：2024-04-25

申请号：US17969904

申请日：2022-10-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hitoshi MAEDA ,  Yoshiyuki KAWASHIMA

IPC: H01L29/423 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/4234 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/788 ,  H01L29/792

Abstract: A height of an upper surface of a control gate electrode is lower than a highest position of a lower surface of a silicide layer on a memory gate electrode adjacent to the control gate electrode via an ONO film. As a result, a structure in contact with the ONO film between the control gate electrode and the memory gate electrode is only the control gate electrode and the memory gate electrode made of polysilicon.