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公开(公告)号：US11940857B2
公开(公告)日：2024-03-26
申请号：US18068437
申请日：2022-12-19
Applicant: Rambus Inc.
Inventor： Deborah Lindsey Dressler , Julia Kelly Cline , Wayne Frederick Ellis
IPC: G06F1/28 , G06F1/32 , G06F1/3234 , G06F1/3287 , G06F13/42 , G11C5/06
CPC classification number: G06F1/28 , G06F1/3275 , G06F1/3287 , G06F13/4273 , G11C5/063
Abstract: A multi-element device includes a plurality of memory elements, each of which includes a memory array, access circuitry to control access to the memory array, and power control circuitry. The power control circuitry, which includes one or more control registers for storing first and second control values, controls distribution of power to the access circuitry in accordance with the first control value, and controls distribution of power to the memory array in accordance with the second control value. Each memory element also includes sideband circuitry for enabling a host system to set at least the first control value and the second control value in the one or more control registers.
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公开(公告)号：US09818463B2
公开(公告)日：2017-11-14
申请号：US15390681
申请日：2016-12-26
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Ely K. Tsern , Brian S. Leibowitz , Wayne Frederick Ellis , Akash Bansal , John Welsford Brooks , Kishore Ven Kasamsetty
CPC classification number: G11C8/18 , G06F13/161 , G06F13/1647 , G06F13/1657 , G06F13/4234 , G11C5/02 , G11C5/04 , G11C7/10 , G11C7/1072 , G11C29/023 , G11C29/028 , G11C2207/2254
Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.
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公开(公告)号：US20240288922A1
公开(公告)日：2024-08-29
申请号：US18610792
申请日：2024-03-20
Applicant: Rambus Inc.
Inventor： Deborah Lindsey Dressler , Julia Kelly Cline , Wayne Frederick Ellis
IPC: G06F1/28 , G06F1/3234 , G06F1/3287 , G06F13/42 , G11C5/06
CPC classification number: G06F1/28 , G06F1/3275 , G06F1/3287 , G06F13/4273 , G11C5/063
Abstract: A multi-element device includes a plurality of memory elements, each of which includes a memory array, access circuitry to control access to the memory array, and power control circuitry. The power control circuitry, which includes one or more control registers for storing first and second control values, controls distribution of power to the access circuitry in accordance with the first control value, and controls distribution of power to the memory array in accordance with the second control value. Each memory element also includes sideband circuitry for enabling a host system to set at least the first control value and the second control value in the one or more control registers.
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公开(公告)号：US11531386B2
公开(公告)日：2022-12-20
申请号：US16915934
申请日：2020-06-29
Applicant: Rambus Inc.
Inventor： Deborah Lindsey Dressler , Julia Kelly Cline , Wayne Frederick Ellis
IPC: G06F1/28 , G06F1/32 , G11C5/06 , G06F1/3287 , G06F1/3234 , G06F13/42
Abstract: A multi-element device includes a plurality of memory elements, each of which includes a memory array, access circuitry to control access to the memory array, and power control circuitry. The power control circuitry, which includes one or more control registers for storing first and second control values, controls distribution of power to the access circuitry in accordance with the first control value, and controls distribution of power to the memory array in accordance with the second control value. Each memory element also includes sideband circuitry for enabling a host system to set at least the first control value and the second control value in the one or more control registers.
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公开(公告)号：US09824752B2
公开(公告)日：2017-11-21
申请号：US15206616
申请日：2016-07-11
Applicant: Rambus Inc.
Inventor： Deepak Chandra Sekar , Wayne Frederick Ellis
IPC: G11C13/00 , G11C11/419 , G11C11/16 , G11C5/06 , G11C5/02
CPC classification number: G11C13/004 , G11C5/02 , G11C5/06 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C13/0002 , G11C13/003 , G11C13/0069 , G11C13/0097 , G11C2013/0071 , G11C2013/0088 , G11C2213/79 , G11C2213/82
Abstract: A memory device includes an array of resistive memory cells wherein each pair of resistive memory cells includes a first switching element electrically coupled in series to a first resistive memory element and a second switching element electrically coupled in series to a second resistive memory element. A source of the first switching element and a source of the second switching element receive a common source line signal.
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Patent Agency Ranking
公开(公告)号：US20170004879A1
公开(公告)日：2017-01-05
申请号：US15206616
申请日：2016-07-11
Applicant: Rambus Inc.
Inventor： Deepak Chandra Sekar , Wayne Frederick Ellis
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C5/02 , G11C5/06 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C13/0002 , G11C13/003 , G11C13/0069 , G11C13/0097 , G11C2013/0071 , G11C2013/0088 , G11C2213/79 , G11C2213/82
Abstract: A memory device includes an array of resistive memory cells wherein each pair of resistive memory cells includes a first switching element electrically coupled in series to a first resistive memory element and a second switching element electrically coupled in series to a second resistive memory element. A source of the first switching element and a source of the second switching element receive a common source line signal.
Abstract translation: 存储器件包括电阻存储器单元阵列，其中每对电阻存储器单元包括与第一电阻存储器元件串联电耦合的第一开关元件和与第二电阻存储元件串联电耦合的第二开关元件。 第一开关元件的源极和第二开关元件的源接收公共源极线信号。
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公开(公告)号：US20230297151A1
公开(公告)日：2023-09-21
申请号：US18068437
申请日：2022-12-19
Applicant: Rambus Inc.
Inventor： Deborah Lindsey Dressler , Julia Kelly Cline , Wayne Frederick Ellis
IPC: G06F1/28 , G11C5/06 , G06F1/3287 , G06F1/3234 , G06F13/42
CPC classification number: G06F1/28 , G06F1/3275 , G06F1/3287 , G06F13/4273 , G11C5/063
Abstract: A multi-element device includes a plurality of memory elements, each of which includes a memory array, access circuitry to control access to the memory array, and power control circuitry. The power control circuitry, which includes one or more control registers for storing first and second control values, controls distribution of power to the access circuitry in accordance with the first control value, and controls distribution of power to the memory array in accordance with the second control value. Each memory element also includes sideband circuitry for enabling a host system to set at least the first control value and the second control value in the one or more control registers.
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公开(公告)号：US09563597B2
公开(公告)日：2017-02-07
申请号：US14386561
申请日：2012-12-20
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Ely K. Tsern , Brian S. Leibowitz , Wayne Frederick Ellis , Akash Bansal , John Welsford Brooks , Kishore Ven Kasamsetty
CPC classification number: G11C8/18 , G06F13/161 , G06F13/1647 , G06F13/1657 , G06F13/4234 , G11C5/02 , G11C5/04 , G11C7/10 , G11C7/1072 , G11C29/023 , G11C29/028 , G11C2207/2254
Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.
Abstract translation: 在允许每个等级的时钟分配树被允许在宽范围内漂移的多存储器存储器系统（例如，低功率存储器系统）中，通过使用引起每个寻址的技术来促进等级之间的命令的精细交错 排名适当地采样旨在该等级的命令，尽管有漂移。 执行这种“微线程”的能力提供了显着增强的存储器容量，而不牺牲单级系统的性能。 本公开提供了适于这些目的的方法，存储器控制器，存储器件和系统设计。
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9.发明申请公开(公告)号：US20160231795A1
公开(公告)日：2016-08-11
申请号：US15017395
申请日：2016-02-05
Applicant: Rambus Inc.
Inventor： Deborah Lindsey Dressler , Julia Kelly Cline , Wayne Frederick Ellis
CPC classification number: G06F1/28 , G06F1/3275 , G06F1/3287 , G06F13/4273 , G11C5/063
Abstract: A multi-element device includes a plurality of memory elements, each of which includes a memory array, access circuitry to control access to the memory array, and power control circuitry. The power control circuitry, which includes one or more control registers for storing first and second control values, controls distribution of power to the access circuitry in accordance with the first control value, and controls distribution of power to the memory array in accordance with the second control value. Each memory element also includes sideband circuitry for enabling a host system to set at least the first control value and the second control value in the one or more control registers.
Abstract translation: 多元件装置包括多个存储器元件，每个存储器元件包括存储器阵列，用于控制对存储器阵列的访问的访问电路和功率控制电路。 包括用于存储第一和第二控制值的一个或多个控制寄存器的功率控制电路根据第一控制值控制对接入电路的功率分配，并且根据第二控制值控制对存储器阵列的功率分配 控制值。 每个存储器元件还包括边带电路，用于使主机系统能够至少设置一个或多个控制寄存器中的第一控制值和第二控制值。
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公开(公告)号：US09390798B2
公开(公告)日：2016-07-12
申请号：US14567988
申请日：2014-12-11
Applicant: Rambus Inc.
Inventor： Deepak Chandra Sekar , Wayne Frederick Ellis
CPC classification number: G11C13/004 , G11C5/02 , G11C5/06 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C13/0002 , G11C13/003 , G11C13/0069 , G11C13/0097 , G11C2013/0071 , G11C2013/0088 , G11C2213/79 , G11C2213/82
Abstract: A memory device includes an array of resistive memory cells wherein each pair of resistive memory cells includes a first switching element electrically coupled in series to a first resistive memory element and a second switching element electrically coupled in series to a second resistive memory element. A source of the first switching element and a source of the second switching element receive a common source line signal.
Abstract translation: 存储器件包括电阻存储器单元阵列，其中每对电阻存储器单元包括与第一电阻存储器元件串联电耦合的第一开关元件和与第二电阻存储元件串联电耦合的第二开关元件。 第一开关元件的源极和第二开关元件的源接收公共源极线信号。
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