公开(公告)号：US11557631B2

公开(公告)日：2023-01-17

申请号：US17088168

申请日：2020-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilho Lee ,  Gwanhyeob Koh ,  Ilmok Park ,  Junhee Lim

IPC: H01L27/24 ,  H01L27/1157 ,  G11C11/16 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/22 ,  H01L27/11575 ,  G11C14/00 ,  G11C5/02 ,  G11C16/04

Abstract: Disclosed is a semiconductor device including first conductive lines, second conductive lines crossing the first conductive lines, and memory cells at intersections between the first conductive lines and the second conductive lines. Each of the memory cells includes a magnetic tunnel junction pattern, a bi-directional switching pattern connected in series to the magnetic tunnel junction pattern, and a conductive pattern between the magnetic tunnel junction pattern and the bi-directional switching pattern.

公开(公告)号：US11437432B2

公开(公告)日：2022-09-06

申请号：US17028034

申请日：2020-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kilho Lee ,  Gwanhyeob Koh ,  Woojin Kim

IPC: H01L27/22 ,  H01L23/522 ,  H01L21/768 ,  H01L43/12

Abstract: An embedded device includes a first insulation layer, a second insulation layer on the first insulation layer, a lower electrode contact in the first insulation layer in a first region, a first structure, having a lower electrode, a magnetic tunnel junction, and an upper electrode, in the second insulation layer and contacting the lower electrode contact, a first metal wiring structure through the first and second insulation layers in a second region, a third insulation layer on the second insulation layer, a bit line structure through the third insulation layer and the second insulation layer in the first region, the bit line structure having a first height and contacting the upper electrode, and a second metal wiring structure through the third insulation layer in the second region, the second metal wiring structure contacting the first metal wiring structure, and having a second height lower than the first height.

公开(公告)号：US11361798B2

公开(公告)日：2022-06-14

申请号：US16411106

申请日：2019-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilho Lee ,  Gwanhyeob Koh ,  Junhee Lim ,  Hongsoo Kim ,  Chang-hoon Jeon

IPC: G11C5/06 ,  G11C16/04 ,  G11C11/16 ,  H01L25/18 ,  H01L27/22 ,  H01L27/11573 ,  H01L43/10 ,  H01L27/1157 ,  G11C13/00 ,  G11C11/00 ,  H01L27/11582

Abstract: A first memory section is disposed on a substrate. A second memory section is vertically stacked on the first memory section. The first memory section is provided between the substrate and the second memory section. The first memory section includes a flash memory cell structure, and the second memory section includes a variable resistance memory cell structure. The flash memory cell structure includes at least one cell string comprising a plurality of first memory cells connected in series to each other and a bit line on the substrate connected to the at least one cell string. The bit line is interposed vertically between the at least one cell string and the second memory section and connected to the second memory section.

公开(公告)号：US10720211B2

公开(公告)日：2020-07-21

申请号：US16458594

申请日：2019-07-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo Kim ,  Bong-Soo Kim ,  Youngbae Kim ,  Kijae Hur ,  Gwanhyeob Koh ,  Hyeongsun Hong ,  Yoosang Hwang

IPC: H01L27/00 ,  G11C14/00 ,  H01L27/24 ,  H01L23/528 ,  G11C13/00 ,  G11C5/02 ,  G11C11/00 ,  H01L45/00 ,  H01L27/108

Abstract: A semiconductor device includes: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed on a substrate; and a second memory section and a wiring section that are stacked on the second peripheral circuit section, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, and the wiring section includes a plurality of line patterns, wherein the line patterns and the second memory cells are higher than the capacitor with respect to the substrate.

公开(公告)号：US10388629B2

公开(公告)日：2019-08-20

申请号：US15718535

申请日：2017-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeshik Kim ,  Gwanhyeob Koh

IPC: H01L25/065 ,  H01L43/08 ,  H01L23/522 ,  H01L27/22 ,  H01L25/00 ,  H01L23/00

Abstract: A semiconductor device comprises a first semiconductor chip comprising a first substrate. A first magnetic tunnel junction is on the first substrate. A second semiconductor chip comprises a second substrate. A second magnetic tunnel junction is on the second substrate. The second semiconductor chip is positioned on the first semiconductor chip to form a chip stack. A first critical current density required for magnetization reversal of the first magnetic tunnel junction is different than a second critical current density required for magnetization reversal of the second magnetic tunnel junction.

公开(公告)号：US20190027200A1

公开(公告)日：2019-01-24

申请号：US15984914

申请日：2018-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungwoo Kim ,  Bong-Soo Kim ,  Youngbae Kim ,  Kijae Hur ,  Gwanhyeob Koh ,  Hyeongsun Hong ,  Yoosang Hwang

IPC: G11C11/00 ,  H01L27/108 ,  H01L27/24 ,  H01L23/528 ,  H01L49/02 ,  H01L45/00

CPC classification number: G11C11/005 ,  G11C5/025 ,  G11C14/0045 ,  H01L23/528 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10897 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2463 ,  H01L28/60 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

Abstract: A semiconductor device including: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed next to each other on a substrate; and a second memory section laterally spaced apart from the first memory section, the second peripheral circuit section and the second memory section disposed next to each other on the substrate, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, and the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, wherein the second memory cells are higher from the substrate than each of the capacitors.

公开(公告)号：US20240349621A1

公开(公告)日：2024-10-17

申请号：US18752866

申请日：2024-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjae Kim ,  Kuhoon Chung ,  Gwanhyeob Koh ,  Bae-Seong Kwon ,  Kyungtae Nam

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/20 ,  H10N50/01

Abstract: A magnetic memory device includes a lower contact plug on a substrate and a data storage structure on the lower contact plug. The data storage structure includes a bottom electrode, a magnetic tunnel junction pattern, and a top electrode that are sequentially stacked on the lower contact plug. The lower contact plug and the data storage structure have a first thickness and a second thickness, respectively, in a first direction perpendicular to a top surface of the substrate. The first thickness of the lower contact plug is about 2.0 to 3.6 times the second thickness of the data storage structure.

公开(公告)号：US10897006B2

公开(公告)日：2021-01-19

申请号：US16286718

申请日：2019-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kilho Lee ,  Gwanhyeob Koh ,  Yongjae Kim ,  Yoonjong Song

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12

Abstract: A magnetic memory device including a substrate including a cell region and a peripheral circuit region; a first interlayer insulating layer covering the cell region and the peripheral circuit region of the substrate; interconnection lines in the first interlayer insulating layer; a peripheral conductive line and a peripheral conductive contact on the first interlayer insulating layer on the peripheral circuit region, the peripheral conductive contact being between the peripheral conductive line and a corresponding one of the interconnection lines; a bottom electrode contact on the first interlayer insulating layer on the cell region and connected to a corresponding one of the interconnection lines; and a data storage pattern on the bottom electrode contact, wherein the peripheral conductive line is at a height between a top surface of the bottom electrode contact and a bottom surface of the bottom electrode contact.

公开(公告)号：US10693055B2

公开(公告)日：2020-06-23

申请号：US16202360

申请日：2018-11-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilho Lee ,  Gwanhyeob Koh ,  Yoonjong Song

IPC: H01L43/02 ,  H01L43/12 ,  H01L43/10 ,  H01L27/22

Abstract: Magnetic random access memory (MRAM) devices are provided. The MRAM devices may include a magnetic tunnel junction (MTJ) including a free layer and a pinned layer sequentially stacked in a vertical direction and a conductive layer adjacent to the free layer of the MTJ. The conductive layer may include a horizontal portion and first and second protruding portions that protrude away from the horizontal portion and are spaced apart from each other in a horizontal direction that is perpendicular to the vertical direction. A side of the free layer and a side of the horizontal portion may form a straight side.

公开(公告)号：US10515678B2

公开(公告)日：2019-12-24

申请号：US16285295

申请日：2019-02-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Boyoung Seo ,  Seongui Seo ,  Gwanhyeob Koh ,  Yongkyu Lee

IPC: G11C11/16 ,  H01L27/22

Abstract: A magnetic memory device includes a substrate, a landing pad on the substrate, first and second magnetic tunnel junction patterns disposed on the interlayer insulating layer and spaced apart from the landing pad when viewed from a plan view, and an interconnection structure electrically connecting a top surface of the second magnetic tunnel junction pattern to the landing pad. A distance between the landing pad and the first magnetic tunnel junction pattern is greater than a distance between the first and second magnetic tunnel junction patterns, and a distance between the landing pad and the second magnetic tunnel junction pattern is greater than the distance between the first and second magnetic tunnel junction patterns, when viewed from a plan view.