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公开(公告)号：US12068015B2
公开(公告)日：2024-08-20
申请号：US17894554
申请日：2022-08-24
发明人： Gyuseong Kang , Hyuntaek Jung
CPC分类号： G11C11/1675 , G11C8/10 , G11C11/1655 , G11C11/1657
摘要： A memory device including a memory cell array including a first sub memory cell array including a first memory cell and a second sub memory cell array including a second memory cell, a merged write driver including a first write circuit receiving n-bit data (n being a natural number ≥2) through a write input/output line, outputting a first write voltage to a merged node in response to a first data bit of the n-bit data, and outputting a second write voltage to the merged node in response to a second data bit of the n-bit data, and a column decoder including a first column multiplexer applying a first voltage of the merged node corresponding to the first data bit to the first memory cell and a second column multiplexer applying a second voltage of the merged node corresponding to the second data bit to the second memory cell.
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公开(公告)号：US11908503B2
公开(公告)日：2024-02-20
申请号：US17711297
申请日：2022-04-01
发明人： Gyuseong Kang , Antonyan Artur , Hyuntaek Jung
CPC分类号： G11C11/1673 , G11C7/1039 , G11C7/14 , G11C11/1655 , G11C11/1675 , G11C11/1697
摘要： A nonvolatile memory device includes an array of magnetic memory cells, and control logic circuit having a voltage generator therein, which is configured to generate a gate voltage. A row decoder is provided, which is connected by word lines to the array of magnetic memory cells, and has a word line driver driven therein, which is responsive to the gate voltage. A column decoder is provided, which is connected by bit lines and source lines to the array of magnetic memory cells. A write driver is provided, which has a write voltage generating circuit therein that is configured to output a write voltage, in response to: (i) a reference voltage generated using a replica magnetic memory cell, and (ii) a feedback voltage generated using a magnetic memory cell in which a write operation is to be performed.
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公开(公告)号：US20230020262A1
公开(公告)日：2023-01-19
申请号：US17711297
申请日：2022-04-01
发明人： Gyuseong Kang , Antonyan Artur , Hyuntaek Jung
摘要： A nonvolatile memory device includes an array of magnetic memory cells, and control logic circuit having a voltage generator therein, which is configured to generate a gate voltage. A row decoder is provided, which is connected by word lines to the array of magnetic memory cells, and has a word line driver driven therein, which is responsive to the gate voltage. A column decoder is provided, which is connected by bit lines and source lines to the array of magnetic memory cells. A write driver is provided, which has a write voltage generating circuit therein that is configured to output a write voltage, in response to: (i) a reference voltage generated using a replica magnetic memory cell, and (ii) a feedback voltage generated using a magnetic memory cell in which a write operation is to be performed.
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公开(公告)号：US10593402B2
公开(公告)日：2020-03-17
申请号：US16243796
申请日：2019-01-09
发明人： Suk-Soo Pyo , Hyuntaek Jung , Taejoong Song , Boyoung Seo
摘要： A nonvolatile memory device includes a first variable resistance element connected to a first bit line, and a first transmission ;ate connected between the first variable resistance element and a first source line. The first transmission gate includes a first insulating layer formed on a well connected to aground voltage, a first n-channel metal oxide semiconductor (NMOS) transistor formed on the first insulating layer and connected to a first word line, a second insulating layer formed on the well, the second insulating layer being in the same layer as the first insulating layer, and a first p-channel metal oxide semiconductor (PMOS) transistor formed on the second insulating layer and connected to a first write word line.
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公开(公告)号：US20190051351A1
公开(公告)日：2019-02-14
申请号：US15936696
申请日：2018-03-27
发明人： SUK-SOO PYO , Hyuntaek Jung , Taejoong Song
CPC分类号： G11C13/0028 , G11C5/147 , G11C7/14 , G11C7/227 , G11C8/08 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1697 , G11C13/0026 , G11C13/003 , G11C13/0033 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C29/028 , G11C29/50 , G11C2013/0054 , G11C2029/5006 , G11C2213/79 , G11C2213/82
摘要： A nonvolatile memory device includes a memory cell including memory cells and dummy cells, a row decoder connected to the memory cells through word lines, a dummy word line bias circuit connected to the dummy cells through dummy word lines, a write driver and sense amplifier connected to the memory cells through bit lines, and a dummy bit line bias circuit connected to the dummy cells through a dummy bit line. The dummy word line bias circuit is configured to apply a same or a different voltage to respective ones of the dummy word lines to turn off selected dummy cells and adjust a leakage current flowing through the dummy cells; and a leakage current in the memory cells is maintained at a substantially uniform level through adjustment of the leakage current in the dummy cells.
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公开(公告)号：US10192618B2
公开(公告)日：2019-01-29
申请号：US15663416
申请日：2017-07-28
发明人： Suk-Soo Pyo , Hyuntaek Jung , Taejoong Song , Boyoung Seo
IPC分类号： G11C13/00
摘要： An operating method of a nonvolatile memory device includes storing different data in first and second reference cells connected to a word line, checking whether the different data are abnormally stored in the first and second reference cells, and when it is determined that the different data are abnormally stored in the first and second reference cells, swapping the first and second reference cells.
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公开(公告)号：US10910030B2
公开(公告)日：2021-02-02
申请号：US16390170
申请日：2019-04-22
发明人： Artur Antonyan , Hyuntaek Jung , Suk-Soo Pyo
IPC分类号： G11C11/16
摘要： A memory device including a normal memory cell array including a first magneto-resistance memory cell that is connected to a first bit line, a first source line, and a first word line, and configured to receive a selection voltage through the first word line, a monitor memory cell array including a second magneto-resistance memory cell that is connected to a first signal line and a second signal line, a gate of a cell transistor of which is configured to receive a non-selection voltage, and a body bias generator configured to sense a leakage current flowing through the first signal line and control a body voltage provided to each of a body of a cell transistor of the first magneto-resistance memory cell and a body of the cell transistor of the second magneto-resistance memory cell based on the leakage current may be provided.
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公开(公告)号：US10431300B2
公开(公告)日：2019-10-01
申请号：US15936696
申请日：2018-03-27
发明人： Suk-Soo Pyo , Hyuntaek Jung , Taejoong Song
IPC分类号： G11C11/00 , G11C13/00 , G11C29/50 , G11C11/16 , G11C5/14 , G11C29/02 , G11C7/14 , G11C8/08 , G11C7/22
摘要： A memory device includes a delay locked loop that generates a first code for delaying a reference clock in a first operation mode that is a normal operation mode, generates a second code for delaying the reference clock in a second operation mode that is a refresh mode, and delays the reference clock in response to one of the first and second codes depending on one of the first and second operation modes, and a data output circuit that outputs a data strobe signal (DQS) using the delayed reference clock.
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