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    SEMICONDUCTOR MEMORY DEVICE
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20250040140A1

    公开(公告)日：2025-01-30

    申请号：US18603505

    申请日：2024-03-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ju Seong MIN ,  Jun Gyeom KIM ,  Hyun Min KIM ,  Kang-Oh YUN ,  Taek Kyu YOON ,  Dong Jin LEE ,  Jae Duk LEE ,  Jee Hoon HAN

    IPC: H10B43/40 ,  G11C5/06 ,  G11C16/04 ,  H01L25/065 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

    Abstract: A semiconductor memory device comprises a cell structure and a peripheral circuit structure electrically connected to the cell structure. The peripheral circuit structure comprises an active region, a first gate structure comprising a first gate insulating layer intersecting the active region and in contact with the active region, a second gate structure comprising a second gate insulating layer spaced apart from the first gate structure, and in contact with the active region, and a source/drain region between the first gate structure and the second gate structure. A thickness of the first gate insulating layer is less than a thickness of the second gate insulating layer. The source/drain region comprises a first region adjacent to the first gate structure and a second region adjacent to the second gate structure. A depth of the first region is equal to a depth of the second region.

    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE
    3.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210143176A1

    公开(公告)日：2021-05-13

    申请号：US17152883

    申请日：2021-01-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jang Gn YUN ,  Jae Duk LEE

    IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524

    Abstract: A three-dimensional semiconductor device includes a stacked structure on a lower structure, the stacked structure including a lower group including gate electrodes vertically stacked and spaced apart from each other, and an upper group including gate electrodes vertically stacked and spaced apart, the lower group and the upper group being vertically stacked, and a vertical structure passing through the stacked structure. The vertical structure may include a vertical core pattern, a vertical buffer portion therein, and a surrounding vertical semiconductor layer, the vertical structure may include a lower vertical portion passing through the lower group and an upper vertical portion passing through the upper group, an upper region of the lower vertical portion may have a width greater than that of a lower region of the upper vertical portion. The vertical buffer portion may be in the lower vertical portion and below the upper vertical portion.

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20250120082A1

    公开(公告)日：2025-04-10

    申请号：US18983846

    申请日：2024-12-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byung Chul JANG ,  Sang-Yong PARK ,  Jae Duk LEE

    IPC: H10B43/27 ,  H10B43/10 ,  H10B43/40

    Abstract: A semiconductor memory device includes a stacked structure on a substrate and a vertical structure penetrating the stacked structure. The stacked structured includes a plurality of conductive lines stacked on the substrate. The vertical structure may include a vertical insulating pattern and a channel film extending along sidewalls of the vertical insulating pattern. The vertical insulating pattern may include an inner region and an outer region. The outer region of the vertical insulating pattern may be placed between the channel film and the inner region of the vertical insulating pattern, and the outer region of the vertical insulating pattern may include a diffused metal.

    NON-VOLATILE MEMORY DEVICE
    6.
    发明申请
    NON-VOLATILE MEMORY DEVICE 有权

    公开(公告)号：US20220076727A1

    公开(公告)日：2022-03-10

    申请号：US17233858

    申请日：2021-04-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Gu Yeon HAN ,  Jin-Kyu KANG ,  Rae Young LEE ,  Se Jun PARK ,  Jae Duk LEE

    IPC: G11C11/4072 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4074

    Abstract: A non-volatile memory device including: a memory cell array including non-volatile memory blocks connected to a plurality of word lines, a plurality of bit lines and a common source line; a common source line driver configured to supply a common source line voltage to the common source line; a page buffer unit configured to supply a bit line voltage to at least one of the plurality of bit lines; a control logic circuit configured to adjust the common source line voltage and the bit line voltage; and a channel initialization circuit, wherein the channel initialization circuit sets the common source line voltage and the bit line voltage to an initialization pulse, and the channel initialization circuit applies the initialization pulse between a plurality of read sections in which a read voltage is applied to at least two of the plurality of word lines.

    SEMICONDUCTOR MEMORY DEVICE, METHOD FOR FABRICATING THE SAME AND ELECTRONIC SYSTEM INCLUDING THE SAME
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE, METHOD FOR FABRICATING THE SAME AND ELECTRONIC SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20250098172A1

    公开(公告)日：2025-03-20

    申请号：US18773994

    申请日：2024-07-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hak Seon KIM ,  Kang Oh YUN ,  Dong Jin LEE ,  Jae Duk LEE

    IPC: H10B43/40 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B43/27 ,  H10B80/00

    Abstract: A semiconductor memory device includes a peripheral circuit structure; and a cell structure including a cell substrate and a gate electrode, on the peripheral circuit structure. The peripheral circuit structure includes a peripheral circuit board including a first surface facing the cell structure and a second surface opposite to the first surface, a first circuit element on the first surface of the peripheral circuit board, a first wiring line electrically connected to the first circuit element in a first interlayer insulating layer, a capacitor dielectric layer covering the second surface of the peripheral circuit board, a first capacitor electrode in the capacitor dielectric layer, a second capacitor electrode spaced apart from the first capacitor electrode in the capacitor dielectric layer, and a first connection via electrically connecting the first capacitor electrode with the first wiring line by passing through the peripheral circuit board.

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