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    SEMICONDUCTOR DEVICE
    4.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230145260A1

    公开(公告)日：2023-05-11

    申请号：US17831513

    申请日：2022-06-03

    Applicant: SAMSUNG ELECTRONICS CO.,LTD.

    Inventor： Yang Xu ,  Nam Kyu Cho ,  Seok Hoon Kim ,  Yong Seung Kim ,  Pan Kwi Park ,  Dong Suk Shin ,  Sang Gil Lee ,  Si Hyung Lee

    IPC: H01L29/78 ,  H01L29/417 ,  H01L29/06

    CPC classification number: H01L29/7851 ,  H01L29/0649 ,  H01L29/41791

    Abstract: A semiconductor device including: a plurality of fin-shaped patterns spaced apart from each other in a first direction and extending in a second direction on a substrate; a field insulating layer covering sidewalls of the plurality of fin-shaped patterns and disposed between the fin-shaped patterns; a source/drain pattern connected to the plurality of fin-shaped patterns on the field insulating layer, the source/drain pattern including bottom surfaces respectively connected to the fin-shaped patterns, and at least one connection surface connecting the bottom surfaces to each other; and a sealing insulating pattern extending along the connection surface of the source/drain pattern and an upper surface of the field insulating layer, wherein the source/drain pattern includes a silicon-germanium pattern doped with a p-type impurity.

    MULTI-CHANNEL FIELD EFFECT TRANSISTORS WITH ENHANCED MULTI-LAYERED SOURCE/DRAIN REGIONS
    5.
    发明公开
    MULTI-CHANNEL FIELD EFFECT TRANSISTORS WITH ENHANCED MULTI-LAYERED SOURCE/DRAIN REGIONS 审中-公开

    公开(公告)号：US20230141852A1

    公开(公告)日：2023-05-11

    申请号：US17866966

    申请日：2022-07-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sanggil Lee ,  Jungtaek Kim ,  Dohyun Go ,  Pankwi Park ,  Dongsuk Shin ,  Namkyu Cho ,  Ryong Ha ,  Yang Xu

    IPC: H01L29/78 ,  H01L29/08 ,  H01L21/8238 ,  H01L27/092

    CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L21/823814 ,  H01L27/0922

    Abstract: A semiconductor device includes a semiconductor active region having a vertical stack of multiple spaced-apart semiconductor channel regions thereon. A gate electrode extends on the active region and between the spaced-apart channel regions. A source/drain region contacts the spaced-apart channel regions. The source/drain region includes a stack of at least first, second and third epitaxial layers having different electrical characteristics. The first epitaxial layer contacts the active region and each of the spaced-apart channel regions. The second epitaxial layer contacts a first portion of an upper surface of the first epitaxial layer. The third epitaxial layer contacts a second portion of the upper surface of the first epitaxial layer. Each of the first, second and third epitaxial layers includes silicon germanium (SiGe) with unequal levels of germanium (Ge) therein. A level of germanium in the third epitaxial layer exceeds a level of germanium in the second epitaxial layer, which exceeds a level of germanium in the first epitaxial layer.

    Semiconductor devices and methods of manufacturing the same
    6.
    发明授权
    Semiconductor devices and methods of manufacturing the same 有权

    公开(公告)号：US11239344B2

    公开(公告)日：2022-02-01

    申请号：US16686378

    申请日：2019-11-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyun Kwan Yu ,  Seung Hun Lee ,  Yang Xu

    IPC: H01L29/66 ,  H01L29/165 ,  H01L29/201 ,  H01L29/20

    Abstract: A method of manufacturing a semiconductor device, the method including: forming, in a first region of a substrate, an active fin and a sacrificial gate structure intersecting the active fin; forming a first spacer and a second spacer on the substrate to cover the sacrificial gate structure; forming a mask in a second region of the substrate to expose the first region of the substrate; removing the second spacer from the first spacer in the first region of the substrate by using the mask; forming recesses at opposite sides of the sacrificial gate structure by removing portions of the active fin; forming a source and a drain in the recesses; and forming an etch-stop layer to cover both sidewalls of the sacrificial gate structure and a top surfaces of the source and drain.

    Semiconductor devices and methods of manufacturing the same
    8.
    发明授权
    Semiconductor devices and methods of manufacturing the same 有权

    公开(公告)号：US10068993B2

    公开(公告)日：2018-09-04

    申请号：US15871479

    申请日：2018-01-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JinBum Kim ,  Kang Hun Moon ,  Choeun Lee ,  Sujin Jung ,  Yang Xu

    IPC: H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/78

    Abstract: Methods of forming an integrated circuit device are provided. The methods may include forming a gate structure on a substrate, forming a first etch mask on a sidewall of the gate structure, anisotropically etching the substrate using the gate structure and the first etch mask as an etch mask to form a preliminary recess in the substrate, forming a sacrificial layer in the preliminary recess, forming a second etch mask on the first etch mask, etching the sacrificial layer and the substrate beneath the sacrificial layer using the gate structure and the first and second etch masks as an etch mask to form a source/drain recess in the substrate, and forming a source/drain in the source/drain recess. A sidewall of the source/drain recess may be recessed toward the gate structure relative to an outer surface of the second etch mask.

    Semiconductor devices
    10.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US12062662B2

    公开(公告)日：2024-08-13

    申请号：US18142210

    申请日：2023-05-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yang Xu ,  Hyunkwan Yu ,  Namkyu Cho ,  Dongmyoung Kim ,  Kanghun Moon ,  Sanggil Lee ,  Sihyung Lee

    IPC: H01L27/092 ,  H01L29/78

    CPC classification number: H01L27/0924 ,  H01L29/7851

    Abstract: A semiconductor device includes a plurality of active fins extending in a first direction, and spaced apart from each other in a second direction, the plurality of active fins having upper surfaces of different respective heights, a gate structure extending in the second across the plurality of active fins, a device isolation film on the substrate, a source/drain region on the plurality of active fins, and including an epitaxial layer on the plurality of active fins, an insulating spacer on an upper surface of the device isolation film and having a lateral asymmetry with respect to a center line of the source/drain region in a cross section taken along the second direction, an interlayer insulating region on the device isolation film and on the gate structure and the source/drain region, and a contact structure in the interlayer insulating region and electrically connected to the source/drain region.

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