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    Tunable and Scalable Command/Address Protocol for Non-Volatile Memory
    3.
    发明申请
    Tunable and Scalable Command/Address Protocol for Non-Volatile Memory 有权

    公开(公告)号：US20220066958A1

    公开(公告)日：2022-03-03

    申请号：US17008553

    申请日：2020-08-31

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Sneha Bhatia ,  Vinayak Ghatawade

    IPC: G06F13/16

    Abstract: A data storage system includes a storage medium including a plurality of memory cells; a storage controller in communication with the storage medium; and an electrical interface between the storage medium and the storage controller. The electrical interface includes an N-bit data bus; a data strobe; a command latch enable signal; and an address latch enable signal; wherein, while the command latch signal or the address latch enable signal is asserted, the storage medium is configured to: (i) receive command or address data via a subset of lines of the data bus; and (ii) latch the command or address data using the data strobe.

    COMPUTING ARCHITECTURE TO PROVIDE SIMPLIFIED POST-SILICON DEBUGGING CAPABILITIES
    6.
    发明申请
    COMPUTING ARCHITECTURE TO PROVIDE SIMPLIFIED POST-SILICON DEBUGGING CAPABILITIES 审中-公开

    公开(公告)号：US20190354369A1

    公开(公告)日：2019-11-21

    申请号：US15979627

    申请日：2018-05-15

    Applicant: SANDISK TECHNOLOGIES, LLC

    Inventor： Vijay Chinchole ,  Vinayak Ghatawade ,  Naman Rastogi

    IPC: G06F9/30 ,  G06F9/38 ,  G06F13/16

    Abstract: This disclosure provides techniques for debugging a computing system in a post-silicon validation process. In one example, a system can include a memory storing a set of instructions. The system can include a controller configured to fetch and execute the set of instructions. The system can include a logic block. The system can include a control bus coupling the memory, the controller, and the logic block. The control bus can include a first break-in circuit and a second break-in circuit each coupled to the controller. The first break-in circuit and the second break-in circuit can be configured to selectively cascade a break point from the controller through the logic block to halt execution of the set of instructions.

    Non-volatile memory interface
    7.
    发明授权
    Non-volatile memory interface 有权

    公开(公告)号：US11048443B1

    公开(公告)日：2021-06-29

    申请号：US16830128

    申请日：2020-03-25

    Applicant: SanDisk Technologies LLC

    Inventor： Sajal Mittal ,  Sneha Bhatia ,  Vinayak Ghatawade

    IPC: G11C16/10 ,  G06F3/06 ,  G06F13/16 ,  G11C16/26 ,  G11C16/08 ,  G06F1/06 ,  G11C16/04

    Abstract: A circuit comprising a non-volatile memory array, an Input/Output (IO) circuit, a decoder circuit, a control circuit, and a read/write circuit. The non-volatile memory array couples to an address decoder that identifies a location within the non-volatile memory array for a storage command. The IO circuit couples to a decoder circuit through a control bus. The decoder circuit decodes a command address and storage command from a fixed length command sequence received by the IO circuit over the data bus. The decoder circuit may include a serial-in parallel out (SIPO) circuit for decoding and parallel operation. The control circuit couples to the IO and decoder circuits and generates control signals to execute decoded storage commands. The read/write circuit couples to the non-volatile memory array and the control circuit. The read/write circuit transfers data between the non-volatile memory array and the IO circuit in response to the storage commands.

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