公开(公告)号：US20240413166A1

公开(公告)日：2024-12-12

申请号：US18805622

申请日：2024-08-15

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Atsushi HIROSE ,  Masashi TSUBUKU ,  Kosei NODA

IPC: H01L27/12 ,  H01L21/8234 ,  H01L27/15 ,  H01L29/24 ,  H01L29/36 ,  H01L29/786 ,  H01L33/00 ,  H01L33/02 ,  H04M1/02 ,  H04R1/02 ,  H10K59/35

Abstract: An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.

公开(公告)号：US20220037153A1

公开(公告)日：2022-02-03

申请号：US17500149

申请日：2021-10-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Miyuki HOSOBA ,  Kosei NODA ,  Hiroki OHARA ,  Toshinari SASAKI ,  Junichiro SAKATA

IPC: H01L21/02 ,  H01L29/66

Abstract: A highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics, and a manufacturing method thereof. In the manufacturing method of the semiconductor device which includes a thin film transistor where a semiconductor layer including a channel formation region is an oxide semiconductor layer, heat treatment which reduces impurities such as moisture to improve the purity of the oxide semiconductor layer and oxidize the oxide semiconductor layer (heat treatment for dehydration or dehydrogenation) is performed. Not only impurities such as moisture in the oxide semiconductor layer but also those existing in a gate insulating layer are reduced, and impurities such as moisture existing in interfaces between the oxide semiconductor layer and films provided over and under and in contact with the oxide semiconductor layer are reduced.

公开(公告)号：US20170317112A1

公开(公告)日：2017-11-02

申请号：US15652312

申请日：2017-07-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Atsushi HIROSE ,  Masashi TSUBUKU ,  Kosei NODA

IPC: H01L27/12 ,  H04M1/02 ,  H01L29/786 ,  H01L29/36 ,  H01L29/24 ,  H01L27/32 ,  H01L27/15 ,  H04R1/02 ,  H01L33/02 ,  H01L21/8234

CPC classification number: H01L27/1225 ,  H01L21/823412 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/156 ,  H01L27/3213 ,  H01L29/24 ,  H01L29/36 ,  H01L29/7869 ,  H01L29/78693 ,  H01L33/025 ,  H01L2924/0002 ,  H04M1/0266 ,  H04R1/02 ,  H01L2924/00

Abstract: An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.

公开(公告)号：US20170278976A1

公开(公告)日：2017-09-28

申请号：US15619670

申请日：2017-06-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kosei NODA ,  Yuta ENDO ,  Toshinari SASAKI

IPC: H01L29/786 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L29/41733

Abstract: A semiconductor device including the following components and a manufacturing method of the semiconductor device are provided. The semiconductor device includes a substrate; an oxide semiconductor layer over the substrate; a source electrode and a drain electrode whose end portion has a taper angle and whose upper end portion has a curved surface, the source electrode and the drain electrode being electrically connected to the oxide semiconductor layer; a gate insulating layer being in contact with a part of the oxide semiconductor layer and covering the oxide semiconductor layer, the source electrode, and the drain electrode; and a gate electrode overlapping with the oxide semiconductor layer and being over the gate insulating layer.

公开(公告)号：US20170236942A1

公开(公告)日：2017-08-17

申请号：US15584242

申请日：2017-05-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO ,  Toshinari SASAKI ,  Kosei NODA

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/477

CPC classification number: H01L29/66969 ,  H01L21/02 ,  H01L21/02112 ,  H01L21/02403 ,  H01L21/28 ,  H01L21/425 ,  H01L21/477 ,  H01L29/42384 ,  H01L29/518 ,  H01L29/78618 ,  H01L29/7869

Abstract: A semiconductor device is manufactured using a transistor in which an oxide semiconductor is included in a channel region and variation in electric characteristics due to a short-channel effect is less likely to be caused. The semiconductor device includes an oxide semiconductor film having a pair of oxynitride semiconductor regions including nitrogen and an oxide semiconductor region sandwiched between the pair of oxynitride semiconductor regions, a gate insulating film, and a gate electrode provided over the oxide semiconductor region with the gate insulating film positioned therebetween. Here, the pair of oxynitride semiconductor regions serves as a source region and a drain region of the transistor, and the oxide semiconductor region serves as the channel region of the transistor.

公开(公告)号：US20160372717A1

公开(公告)日：2016-12-22

申请号：US15176350

申请日：2016-06-08

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kosei NODA

IPC: H01M2/02

CPC classification number: H01M2/026 ,  H01M2/0207 ,  H01M2/0212 ,  H01M2/0275 ,  H01M2/0287 ,  H01M2/06 ,  H01M10/0436 ,  H01M10/0459 ,  H01M2220/30

Abstract: A power storage device with high capacity per unit volume, a flexible power storage device with a novel structure, a repeatedly bendable power storage device, a highly reliable power storage device, or a long-life power storage device is provided. The power storage device includes an inner structure and an exterior body surrounding the inner structure. The inner structure includes a positive electrode and a negative electrode. The exterior body includes a first film containing titanium and one or more elements selected from niobium, tantalum, vanadium, zirconium, and hafnium. It is preferable that the first film further contain one or more elements selected from molybdenum, chromium, and aluminum.

Abstract translation: 提供具有高容量的单位体积的蓄电装置，具有新颖结构的柔性蓄电装置，可重复弯曲的蓄电装置，高可靠性蓄电装置或长寿命蓄电装置。 蓄电装置包括内部结构和围绕内部结构的外部主体。 内部结构包括正极和负极。 外壳包括含有钛和选自铌，钽，钒，锆和铪中的一种或多种元素的第一膜。 优选第一膜还含有一种或多种选自钼，铬和铝的元素。

公开(公告)号：US20160190176A1

公开(公告)日：2016-06-30

申请号：US15063706

申请日：2016-03-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Atsushi HIROSE ,  Masashi TSUBUKU ,  Kosei NODA

IPC: H01L27/12 ,  H04M1/02 ,  H01L27/15 ,  H01L27/32 ,  H01L29/24 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L21/823412 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/156 ,  H01L27/3213 ,  H01L29/24 ,  H01L29/36 ,  H01L29/7869 ,  H01L29/78693 ,  H01L33/025 ,  H01L2924/0002 ,  H04M1/0266 ,  H04R1/02 ,  H01L2924/00

Abstract: An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.

Abstract translation: 目的是获得使用其中使用氧化物半导体层的薄膜晶体管，在检测信号和宽动态范围中具有高灵敏度的半导体器件。 使用具有作为沟道形成层的功能的氧化物半导体的薄膜晶体管形成模拟电路，其氢浓度为5×1019个原子/ cm3以下，并且在该状态下基本上起绝缘体的作用 其中不产生电场。 因此，可以获得在检测信号中具有高灵敏度和宽动态范围的半导体器件。

公开(公告)号：US20160064505A1

公开(公告)日：2016-03-03

申请号：US14935553

申请日：2015-11-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO ,  Toshinari SASAKI ,  Kosei NODA ,  Hitomi SATO ,  Yuhei SATO

IPC: H01L29/49 ,  H01L21/288 ,  H01L21/28 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/4908 ,  H01L21/28088 ,  H01L21/288 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/7869

Abstract: To manufacture a transistor whose threshold voltage is controlled without using a backgate electrode, a circuit for controlling the threshold voltage, and an impurity introduction method. To manufacture a semiconductor device having favorable electrical characteristics, high reliability, and low power consumption using the transistor. A gate electrode including a tungsten oxide film whose composition is controlled is used. The composition or the like is adjusted by a film formation method of the tungsten oxide film, whereby the work function can be controlled. By using the tungsten oxide film whose work function is controlled as part of the gate electrode, the threshold of the transistor can be controlled. Using the transistor whose threshold voltage is controlled, a semiconductor device having favorable electrical characteristics, high reliability, and low power consumption can be manufactured.

Abstract translation: 制造在不使用背栅电极的情况下控制阈值电压的晶体管，用于控制阈值电压的电路和杂质导入方法。 使用晶体管制造具有良好的电特性，高可靠性和低功耗的半导体器件。 使用包含其组成被控制的氧化钨膜的栅电极。 通过氧化钨膜的成膜方法调整组合物等，由此可以控制功函数。 通过使用功函数被控制为栅电极的一部分的氧化钨膜，可以控制晶体管的阈值。 通过使用阈值电压被控制的晶体管，可以制造具有良好的电特性，高可靠性和低功耗的半导体器件。

公开(公告)号：US20150349130A1

公开(公告)日：2015-12-03

申请号：US14723624

申请日：2015-05-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kazuki TANEMURA ,  Tetsuhiro TANAKA ,  Kosei NODA

IPC: H01L29/786 ,  H01L29/51 ,  H01L29/792 ,  H01L27/12 ,  H01L27/088

CPC classification number: H01L29/7869 ,  H01L22/14 ,  H01L22/20 ,  H01L27/0883 ,  H01L27/1104 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/1259 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66969 ,  H01L29/78696 ,  H01L29/792

Abstract: Threshold voltage adjustment method of a semiconductor device is provided. In a semiconductor device in which at least one of transistors included in an inverter includes a semiconductor, a source electrode or a drain electrode electrically connected to the semiconductor, a gate electrode, and a charge trap layer provided between the gate electrode and the semiconductor, the potential of the gate electrode of the transistor that is higher than those of the source electrode and the drain electrode is held for a short time of 5 s or shorter, whereby electrons are trapped in the charge trap layer and the threshold voltage is increased. At this time, when the potential differences between the gate electrode and the source electrode, and the gate electrode and the drain electrode are different from each other, the threshold voltage of the transistor of the semiconductor device becomes appropriate.

Abstract translation: 提供半导体器件的阈值电压调整方法。 在其中包括在反相器中的至少一个晶体管包括半导体，与半导体电连接的源电极或漏电极，设置在栅电极和半导体之间的栅电极和电荷陷阱层的半导体器件中， 晶体管的栅电极的电位比源电极和漏电极的电位保持5秒以下的短时间，由此电子被捕获在电荷陷阱层中，并且阈值电压增加。 此时，当栅电极和源电极以及栅电极和漏电极之间的电位差彼此不同时，半导体器件的晶体管的阈值电压变得适当。

公开(公告)号：US20150097595A1

公开(公告)日：2015-04-09

申请号：US14570553

申请日：2014-12-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Masashi TSUBUKU ,  Kosei NODA

IPC: H03K19/003 ,  H03K19/096

CPC classification number: H01L27/1255 ,  G09G3/20 ,  G09G3/2092 ,  G09G3/3233 ,  G09G3/3291 ,  G09G3/36 ,  G09G3/3648 ,  G09G2300/0439 ,  G09G2300/08 ,  G09G2300/0842 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/184 ,  G11C19/28 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/7869 ,  H03K17/161 ,  H03K19/00315 ,  H03K19/096

Abstract: To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10−13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.

Abstract translation: 为了减小晶体管的漏电流，可以抑制逻辑电路的故障。 逻辑电路包括晶体管，其包括具有沟道形成层的功能的氧化物半导体层，并且其中截止电流在沟道宽度中为每微米1×10-13A或更小。 作为时钟信号的第一信号，第二信号和第三信号被输入作为输入信号。 作为输出信号输出第四信号和第五信号，其电压状态根据输入的第一至第三信号而被设定。