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    Logic circuit formed using unipolar transistor, and semiconductor device
    1.
    发明授权
    Logic circuit formed using unipolar transistor, and semiconductor device 有权

    公开(公告)号：US12040795B2

    公开(公告)日：2024-07-16

    申请号：US17413791

    申请日：2019-12-10

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Hiroki Inoue ,  Munehiro Kozuma ,  Takeshi Aoki ,  Shuji Fukai ,  Fumika Akasawa ,  Shintaro Harada ,  Sho Nagao

    IPC: H03K19/094 ,  H01L27/06

    CPC classification number: H03K19/094 ,  H01L27/0629

    Abstract: A semiconductor device using unipolar transistors, in which high and low levels are expressed using high and low power supply potentials, is provided. The semiconductor device includes four transistors, two capacitors, two wirings, two input terminals, and an output terminal. A source or a drain of the first transistor and a source or a drain of the fourth transistor are electrically connected to the first wiring. A gate of the fourth transistor is electrically connected to the first input terminal, and a gate of the second transistor is electrically connected to the second input terminal. A source or a drain of the second transistor and a source or a drain of the third transistor are electrically connected to the second wiring. The first transistor, the second transistor, and the two capacitors are electrically connected to the output terminal.

    Neural network semiconductor device and system using the same
    3.
    发明授权
    Neural network semiconductor device and system using the same 有权

    公开(公告)号：US11099814B2

    公开(公告)日：2021-08-24

    申请号：US15729150

    申请日：2017-10-10

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shintaro Harada ,  Yoshiyuki Kurokawa ,  Takeshi Aoki

    IPC: G06F7/544 ,  G06N3/063 ,  H01L29/786 ,  G06N3/04

    Abstract: A semiconductor device capable of performing product-sum operation is provided. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. The semiconductor device retains first analog data and reference analog data in the first memory cell and the second memory cell, respectively. A potential corresponding to second analog data is applied to each of them as a selection signal, whereby current depending on the sum of products of the first analog data and the second analog data is obtained. The offset circuit includes a constant current circuit comprising a transistor and a capacitor. A first terminal of the transistor is electrically connected to a first gate of the transistor and a first terminal of the capacitor. A second gate of the transistor is electrically connected to a second terminal of the capacitor. A voltage between the first terminal and the second gate of the transistor is held in the capacitor, whereby a change in source-drain current of the transistor can be suppressed.

    Semiconductor device and electronic device
    8.
    发明授权
    Semiconductor device and electronic device 有权

    公开(公告)号：US12120443B2

    公开(公告)日：2024-10-15

    申请号：US17793104

    申请日：2021-01-08

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yoshiyuki Kurokawa ,  Munehiro Kozuma ,  Takeshi Aoki ,  Takuro Kanemura

    IPC: H04N25/74 ,  H01L27/12 ,  H01L29/786 ,  H10B12/00 ,  H10K39/32

    CPC classification number: H04N25/74 ,  H10K39/32 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/78648 ,  H01L29/7869 ,  H10B12/00

    Abstract: A semiconductor device that has low power consumption and is capable of performing a product-sum operation is provided. The semiconductor device includes first and second cells, a first circuit, and first to third wirings. Each of the first and second cells includes a capacitor, and a first terminal of each of the capacitors is electrically connected to the third wiring. Each of the first and second cells has a function of feeding a current based on a potential held at a second terminal of the capacitor, to a corresponding one of the first and second wirings. The first circuit is electrically connected to the first and second wirings and stores currents I1 and I2 flowing through the first and second wirings. When the potential of the third wiring changes and accordingly the amount of current of the first wiring changes from I1 to I3 and the amount of current of the second wiring changes from I2 to I4, the first circuit generates a current with an amount I1−I2−I3+I4. Note that the potential of the third wiring is changed by firstly inputting a reference potential to the third wiring and then inputting a potential based on internal data or a potential based on information obtained by a sensor.

    Semiconductor device and method for operating semiconductor device
    9.
    发明授权
    Semiconductor device and method for operating semiconductor device 有权

    公开(公告)号：US11916065B2

    公开(公告)日：2024-02-27

    申请号：US17425348

    申请日：2020-02-13

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Kei Takahashi ,  Takeshi Aoki

    IPC: H01L27/06 ,  H01L29/786 ,  H03F3/16 ,  H02J7/00

    CPC classification number: H01L27/0629 ,  H01L29/7869 ,  H03F3/16 ,  H02J7/0029

    Abstract: A novel comparison circuit, a novel amplifier circuit, a novel battery control circuit, a novel battery protection circuit, a power storage device, a semiconductor device, an electronic device, and the like are provided. The semiconductor device includes a capacitor, a first amplifier circuit including a first output terminal electrically connected to a first electrode of the capacitor, and a second amplifier circuit including an input terminal, a second output terminal, a first transistor, and a second transistor; a second electrode of the capacitor is electrically connected to the input terminal; the input terminal is electrically connected to a gate of the first transistor and one of a source and a drain of the second transistor; one of a source and a drain of the first transistor is electrically connected to the second output terminal; the second transistor has a function of supplying a potential to the input terminal and holding the potential; and a channel formation region of the second transistor includes a metal oxide containing at least one of indium and gallium.

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