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35 条记录 (耗时 0.018 秒)

    Memory system and operating method thereof
    1.
    发明授权
    Memory system and operating method thereof 有权

    公开(公告)号：US10818365B2

    公开(公告)日：2020-10-27

    申请号：US16124927

    申请日：2018-09-07

    申请人： SK hynix Inc.

    发明人： Seung-Gyu Jeong ,  Jung-Hyun Kwon ,  Do-Sun Hong ,  Won-Gyu Shin

    IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/34 ,  G11C16/32 ,  G11C16/26 ,  G11C16/10

    摘要： A memory system includes a memory device including a plurality of memory blocks, a first detection block suitable for detecting a hot memory block based on a number of times that a write operation is performed among the memory blocks during the write operation, a second detection block suitable for detecting first memory blocks based on the number of times that the write operation is performed among the memory blocks and detecting a cold memory block based on addresses of the first memory blocks, when the hot memory block is detected, and a wear-leveling block suitable for swapping data of the hot memory block for data of the cold memory block.

    Reducing disturbance between adjacent regions of a memory device
    2.
    发明授权
    Reducing disturbance between adjacent regions of a memory device 有权

    公开(公告)号：US10747448B2

    公开(公告)日：2020-08-18

    申请号：US15598446

    申请日：2017-05-18

    申请人： SK hynix Inc.

    发明人： Jung-Hyun Kwon ,  Sang-Gu Jo ,  Do-Sun Hong

    IPC分类号： G06F3/06 ,  G11C13/00 ,  G06F1/24 ,  G11C7/02

    摘要： A memory system includes a memory device including one or more memory blocks, and configured to store data in a plurality of pages included in each memory block through a write operation, and a memory controller configured to count an operation number of write operations performed on the memory block, check whether the write operation is performed for each of the pages, select one or more victim pages among the pages, and copy data stored in the victim pages.

    Memory system and operation method thereof
    3.
    发明授权
    Memory system and operation method thereof 有权

    公开(公告)号：US10656832B2

    公开(公告)日：2020-05-19

    申请号：US15617109

    申请日：2017-06-08

    申请人： SK hynix Inc.

    发明人： Jung-Hyun Kwon ,  Sung-Eun Lee ,  Sang-Gu Jo

    IPC分类号： G06F3/06 ,  G06F12/02 ,  G06F12/06

    摘要： A memory system comprises a memory device including a plurality of memory blocks, a write operation check unit configured to count the number of write operations performed on the respective memory blocks, a write count distribution management module configured to manage a distribution of the memory blocks based on the counted number of the write operations, and a wear leveling module configured to detect hot and cold memory blocks from the plurality of memory blocks based on the counted number of the write operation and the distribution, wherein the wear leveling module manages a history of the hot memory block and swaps the hot memory block with the cold memory block according to the managed history.

    Memory system
    4.
    发明授权
    Memory system 有权

    公开(公告)号：US10559354B2

    公开(公告)日：2020-02-11

    申请号：US16007538

    申请日：2018-06-13

    申请人： SK hynix Inc.

    发明人： Seung-Gyu Jeong ,  Jung-Hyun Kwon ,  Do-Sun Hong ,  Won-Gyu Shin

    IPC分类号： G11C8/10 ,  G11C13/00

    摘要： A memory system includes: a first cell array including a plurality of memory cells; and a second cell array including a plurality of memory cells; and an address operation circuit suitable for generating a first cell array address, the first cell array address used for accessing at least one first cell in the first cell array, by adding a first value to an address, and generating a second cell array address, the second cell array address used for accessing at least one second cell in the second cell array, by adding a second value to the address.

    Memory device and memory system including the same
    6.
    发明授权
    Memory device and memory system including the same 有权
    存储器件和存储器系统包括相同的

    公开(公告)号：US09196323B2

    公开(公告)日：2015-11-24

    申请号：US14106829

    申请日：2013-12-15

    申请人： SK hynix Inc.

    发明人： Jung-Hyun Kwon

    IPC分类号： G11C7/10

    CPC分类号： G11C7/1066 ,  G11C7/1072 ,  G11C7/1093 ,  G11C7/1096 ,  G11C2207/2254

    摘要： A memory system includes a controller suitable for providing a data to be written on a memory cell array and a control data for indicating whether or not the data has a preset data pattern and a memory device suitable for selectively writing an patterned data or the data provided by the controller on the memory cell array in response to the control data, wherein the patterned data is stored in the memory device and has the preset data pattern.

    摘要翻译： 存储器系统包括适于提供要写入存储器单元阵列的数据的控制器和用于指示数据是否具有预设数据模式的控制数据和适于选择性地写入图案化数据或提供的数据的存储器件 通过响应于控制数据的存储单元阵列上的控制器，其中图案化数据被存储在存储器件中并且具有预设的数据模式。

    Delay circuit and write and read latency control circuit of memory, and signal delay method thereof
    7.
    发明授权
    Delay circuit and write and read latency control circuit of memory, and signal delay method thereof 有权

    公开(公告)号：US10762008B2

    公开(公告)日：2020-09-01

    申请号：US16203591

    申请日：2018-11-28

    申请人： SK hynix Inc.

    发明人： Jung-Hyun Kwon ,  Do-Sun Hong ,  Won-Gyu Shin ,  Seung-Gyu Jeong

    IPC分类号： G06F13/16 ,  G06F3/06

    摘要： A memory module includes a first memory device that includes first circuit nodes for communication with a memory controller and second circuit nodes for communication inside the memory module, a second memory device that includes first circuit nodes for communication with the memory controller and second circuit nodes for communication inside the memory module, and an internal data bus that couples the first memory device to the second memory device to carry data between the second circuit nodes of the first memory device and the second circuit nodes of the second memory device. When an internal read command is applied to the first memory device and an internal write command is applied to the second memory device, data is transferred from the first memory device to the second memory device through the internal data bus.

    Memory system and wear-leveling method thereof
    10.
    发明授权
    Memory system and wear-leveling method thereof 有权

    公开(公告)号：US09990153B2

    公开(公告)日：2018-06-05

    申请号：US15618597

    申请日：2017-06-09

    申请人： SK hynix Inc.

    发明人： Jung-Hyun Kwon ,  Dong-Gun Kim ,  Sang-Gu Jo

    IPC分类号： G06F12/02 ,  G06F3/06

    CPC分类号： G06F3/0619 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/065 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7211

    摘要： A memory system includes a memory device performing write operations on lines included in a memory block among a plurality of memory blocks included in the memory device; a counting unit counting a write count for each of the plurality of memory blocks, and outputting the write counts; a first wear-leveling unit performing a wear leveling operation by shifting the lines of each of the plurality of memory blocks; and a second wear-leveling unit detecting hot and cold memory blocks among the plurality of memory blocks based on the write counts, and swapping the hot memory block with the cold memory block, wherein the second wear-leveling unit selects at least one memory block among the plurality of memory blocks based on the write counts, and checks whether the write operation is performed on each of the lines included in the selected memory block.