公开(公告)号：US09397236B2

公开(公告)日：2016-07-19

申请号：US14021208

申请日：2013-09-09

Applicant: STATS ChipPAC, Ltd.

Inventor： Zigmund R. Camacho ,  Henry D. Bathan ,  Lionel Chien Hui Tay ,  Arnel Senosa Trasporto

IPC: H01L31/02 ,  H01L31/0203 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L31/0203 ,  H01L21/563 ,  H01L23/3121 ,  H01L24/32 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A semiconductor device is made by providing a semiconductor die having an optically active area, providing a leadframe or pre-molded laminated substrate having a plurality of contact pads and a light transmitting material disposed between the contact pads, attaching the semiconductor die to the leadframe so that the optically active area is aligned with the light transmitting material to provide a light transmission path to the optically active area, and disposing an underfill material between the semiconductor die and leadframe. The light transmitting material includes an elevated area to prevent the underfill material from blocking the light transmission path. The elevated area includes a dam surrounding the light transmission path, an adhesive ring, or the light transmission path itself can be the elevated area. An adhesive ring can be disposed on the dam. A filler material can be disposed between the light transmitting material and contact pads.

公开(公告)号：US20140011315A1

公开(公告)日：2014-01-09

申请号：US14021208

申请日：2013-09-09

Applicant: STATS ChipPAC, Ltd.

Inventor： Zigmund R. Camacho ,  Henry D. Bathan ,  Lionel Chien Hui Tay ,  Arnel Senosa Trasporto

IPC: H01L31/0203

CPC classification number: H01L31/0203 ,  H01L21/563 ,  H01L23/3121 ,  H01L24/32 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A semiconductor device is made by providing a semiconductor die having an optically active area, providing a leadframe or pre-molded laminated substrate having a plurality of contact pads and a light transmitting material disposed between the contact pads, attaching the semiconductor die to the leadframe so that the optically active area is aligned with the light transmitting material to provide a light transmission path to the optically active area, and disposing an underfill material between the semiconductor die and leadframe. The light transmitting material includes an elevated area to prevent the underfill material from blocking the light transmission path. The elevated area includes a dam surrounding the light transmission path, an adhesive ring, or the light transmission path itself can be the elevated area. An adhesive ring can be disposed on the dam. A filler material can be disposed between the light transmitting material and contact pads.

Abstract translation: 通过提供具有光学活性区域的半导体管芯制造半导体器件，提供具有多个接触焊盘的引线框架或预成型层叠基板和设置在接触焊盘之间的透光材料，将半导体管芯附接到引线框架 光学活性区域与透光材料对准以提供到光学有效区域的光传输路径，并且在半导体管芯和引线框架之间设置底部填充材料。 透光材料包括用于防止底部填充材料阻挡光传输路径的升高区域。 升高区域包括围绕光传输路径的堤坝，粘合环，或者光传输路径本身可以是高架区域。 可以在大坝上设置粘合环。 填充材料可以设置在透光材料和接触垫之间。

公开(公告)号：US20130256861A1

公开(公告)日：2013-10-03

申请号：US13791375

申请日：2013-03-08

Applicant: STATS CHIPPAC LTD.

Inventor： Byung Tai Do ,  Arnel Senosa Trasporto ,  Linda Pei Ee Chua

IPC: H01L23/28 ,  H01L21/56

CPC classification number: H01L23/28 ,  H01L21/4832 ,  H01L21/56 ,  H01L23/16 ,  H01L23/3107 ,  H01L23/49582 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: An integrated circuit packaging system, and a method of manufacture therefor, including: electrical terminals; circuitry protective material around the electrical terminals and formed to have recessed pad volumes; routable circuitry on the top surface of the circuitry protective material; and an integrated circuit die electrically connected to the electrical terminals.

Abstract translation: 一种集成电路封装系统及其制造方法，包括：电端子; 在电气端子周围的电路保护材料，并形成为具有凹陷垫体积; 电路保护材料顶表面上的可路由电路; 以及与电端子电连接的集成电路管芯。

公开(公告)号：USRE47923E1

公开(公告)日：2020-03-31

申请号：US15058005

申请日：2016-03-01

Applicant: STATS ChipPAC, Ltd.

Inventor： Zigmund R. Camacho ,  Frederick R. Dahilig ,  Lionel Chien Hui Tay ,  Arnel Senosa Trasporto ,  Henry Descalzo Bathan

IPC: H01L23/24 ,  H01L23/28 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L25/03 ,  H01L25/10

Abstract: A PiP semiconductor device has an inner known good semiconductor package. In the semiconductor package, a first via is formed in a temporary carrier. A first conductive layer is formed over the carrier and into the first via. The first conductive layer in the first via forms a conductive bump. A first semiconductor die is mounted to the first conductive layer. A first encapsulant is deposited over the first die and carrier. The semiconductor package is mounted to a substrate. A second semiconductor die is mounted to the first conductive layer opposite the first die. A second encapsulant is deposited over the second die and semiconductor package. A second via is formed in the second encapsulant to expose the conductive bump. A second conductive layer is formed over the second encapsulant and into the second via. The second conductive layer is electrically connected to the second die.

公开(公告)号：US10068862B2

公开(公告)日：2018-09-04

申请号：US15082190

申请日：2016-03-28

Applicant: STATS ChipPAC, Ltd.

Inventor： Byung Tai Do ,  Arnel Senosa Trasporto

IPC: H01L23/48 ,  H01L21/60 ,  H01L23/538 ,  H01L21/56 ,  H01L21/50 ,  H01L23/00 ,  H01L25/00 ,  H01L25/03 ,  H01L25/10 ,  H01L23/498 ,  H01L23/31

Abstract: A semiconductor device comprises a first semiconductor package including a first interconnect structure extending over a surface of the first semiconductor package. The first semiconductor package includes an interposer and a second semiconductor die disposed over the interposer. A second encapsulant is deposited over the interposer and second semiconductor die. A first semiconductor die is disposed over the surface of the first semiconductor package. A second interconnect structure extends from the first semiconductor die opposite the first semiconductor package. A first encapsulant is deposited over the first semiconductor package and first semiconductor die. A portion of the first encapsulant over the first interconnect structure and second interconnect structure is removed. A discrete component is disposed on the surface of the first semiconductor package. A build-up interconnect structure is formed over the first semiconductor package and first semiconductor die. The first semiconductor package includes a molded laser package.

公开(公告)号：US08791556B2

公开(公告)日：2014-07-29

申请号：US13791375

申请日：2013-03-08

Applicant: STATS ChipPAC Ltd.

Inventor： Byung Tai Do ,  Arnel Senosa Trasporto ,  Linda Pei Ee Chua

IPC: H01L23/28 ,  H01L21/56

CPC classification number: H01L23/28 ,  H01L21/4832 ,  H01L21/56 ,  H01L23/16 ,  H01L23/3107 ,  H01L23/49582 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: An integrated circuit packaging system, and a method of manufacture therefor, including: electrical terminals; circuitry protective material around the electrical terminals and formed to have recessed pad volumes; routable circuitry on the top surface of the circuitry protective material; and an integrated circuit die electrically connected to the electrical terminals.

Abstract translation: 一种集成电路封装系统及其制造方法，包括：电端子; 在电气端子周围的电路保护材料，并形成为具有凹陷垫体积; 电路保护材料顶表面上的可路由电路; 以及与电端子电连接的集成电路管芯。

公开(公告)号：US20160300817A1

公开(公告)日：2016-10-13

申请号：US15082190

申请日：2016-03-28

Applicant: STATS ChipPAC, Ltd.

Inventor： Byung Tai Do ,  Arnel Senosa Trasporto

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L21/52

CPC classification number: H01L24/11 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00014

Abstract: A semiconductor device comprises a first semiconductor package including a first interconnect structure extending over a surface of the first semiconductor package. The first semiconductor package includes an interposer and a second semiconductor die disposed over the interposer. A second encapsulant is deposited over the interposer and second semiconductor die. A first semiconductor die is disposed over the surface of the first semiconductor package. A second interconnect structure extends from the first semiconductor die opposite the first semiconductor package. A first encapsulant is deposited over the first semiconductor package and first semiconductor die. A portion of the first encapsulant over the first interconnect structure and second interconnect structure is removed. A discrete component is disposed on the surface of the first semiconductor package. A build-up interconnect structure is formed over the first semiconductor package and first semiconductor die. The first semiconductor package includes a molded laser package.

Abstract translation: 半导体器件包括第一半导体封装，其包括在第一半导体封装的表面上延伸的第一互连结构。 第一半导体封装包括插入件和设置在插入件上的第二半导体管芯。 第二密封剂沉积在插入件和第二半导体管芯上。 第一半导体管芯设置在第一半导体封装的表面上。 第二互连结构从与第一半导体封装相对的第一半导体管芯延伸。 第一密封剂沉积在第一半导体封装和第一半导体管芯上。 去除第一互连结构和第二互连结构上的第一密封剂的一部分。 分立部件设置在第一半导体封装的表面上。 在第一半导体封装和第一半导体管芯上形成积层互连结构。 第一半导体封装包括模制激光器封装。