公开(公告)号：US20160119117A1

公开(公告)日：2016-04-28

申请号：US14986152

申请日：2015-12-31

Applicant: STMicroelectronics International N.V.

Inventor： Abhishek CHOWDHARY ,  Vivek UPPAL ,  Alok KAUSHIK ,  Sajal Kumar MANDAL ,  Tapas NANDY ,  Sanjeev CHOPRA

IPC: H04L7/00 ,  H03L7/08 ,  H04L7/033

CPC classification number: H04L7/0087 ,  H03L7/0807 ,  H03L7/091 ,  H04L7/0004 ,  H04L7/005 ,  H04L7/033 ,  H04L7/0331 ,  H04L7/0338 ,  H04L25/03057 ,  H04L43/022

Abstract: A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter.

公开(公告)号：US20180006797A1

公开(公告)日：2018-01-04

申请号：US15703792

申请日：2017-09-13

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Tapas NANDY ,  Nitin GUPTA

IPC: H04L7/00 ,  H04L5/00 ,  H04L7/033 ,  H04L7/02 ,  G06F1/10 ,  H04L1/00 ,  H04J3/06 ,  H04L7/027

CPC classification number: H04L7/0008 ,  G06F1/10 ,  H04J3/0685 ,  H04L1/0026 ,  H04L5/00 ,  H04L7/02 ,  H04L7/027 ,  H04L7/033 ,  H04L7/0337

Abstract: A source synchronous data transmission system includes a data transmitting device and a data receiving device. A dedicated data line carries a data signal from the data transmission device to the data receiving device. A dedicated clock line carries a modulated clock signal from the data transmission device to the data receiving device. The data transmission device includes a clock data driver configured to encode data into the modulated clock signal by modulating an amplitude of the modulated clock signal. Thus, the clock line of the source synchronous data transmission system carries the clock signal and additional data.

公开(公告)号：US20160187392A1

公开(公告)日：2016-06-30

申请号：US14585357

申请日：2014-12-30

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Daljeet KUMAR ,  Tapas NANDY ,  Surendra KUMAR

IPC: G01R19/04

CPC classification number: G01R19/04 ,  G01R19/2503

Abstract: A data receiving device may include an envelope detector that may include first and second inputs configured to receive a differential input signal, a first pair of detectors coupled to the first input and configured to generate first and second detector outputs, and a second pair of detectors coupled to the second input and configured to generate third and fourth detector outputs. The envelope detector may also include a logic circuit configured to generate a reset based upon the first and third detectors. The data receiving device may also include a receiver circuit coupled to the envelope detector and configured to generate an output based upon the second and fourth detectors along with the reset, and a first bit detection circuit coupled to the receiver circuit.

Abstract translation: 数据接收设备可以包括包络检测器，其可以包括被配置为接收差分输入信号的第一和第二输入，耦合到第一输入并被配置为产生第一和第二检测器输出的第一对检测器，以及第二对检测器 耦合到第二输入并且被配置为产生第三和第四检测器输出。 包络检测器还可以包括被配置为基于第一和第三检测器产生复位的逻辑电路。 数据接收装置还可以包括耦合到包络检测器的接收器电路，并被配置成随着复位产生基于第二和第四检测器的输出，以及耦合到接收器电路的第一位检测电路。

公开(公告)号：US20160149695A1

公开(公告)日：2016-05-26

申请号：US15009696

申请日：2016-01-28

Applicant: STMicroelectronics International N.V.

Inventor： Abhishek CHOWDHARY ,  Vivek UPPAL ,  Alok KAUSHIK ,  Sajal Kumar MANDAL ,  Tapas NANDY ,  Sanjeev CHOPRA

IPC: H04L7/033 ,  H04L12/26

CPC classification number: H04L7/0087 ,  H03L7/0807 ,  H03L7/091 ,  H04L7/0004 ,  H04L7/005 ,  H04L7/033 ,  H04L7/0331 ,  H04L7/0338 ,  H04L25/03057 ,  H04L43/022

Abstract: A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter.

公开(公告)号：US20150341017A1

公开(公告)日：2015-11-26

申请号：US14283043

申请日：2014-05-20

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Nitin GUPTA ,  Paramjeet Singh SAHNI ,  Tapas NANDY ,  Manish GARG

IPC: H03K3/01 ,  H04N5/63 ,  H04N5/44

CPC classification number: H03K3/01 ,  H03K19/018528 ,  H04N5/44 ,  H04N5/63

Abstract: A power harvesting circuit includes a new transmitter topology that ensures that no junction of thin oxide transistors forming the power harvesting circuit will experience a voltage across junctions of the transistors that is more than a maximum tolerable junction voltage. A supplemental power feed circuit operates to provide a supplemental feed current to components in a transmitter circuit when power harvested from a receiver circuit is insufficient to adequately power these components of the transmitter circuit, which may occur during high frequency operation of communications channels coupling the transmitter and receiver circuits. The supplemental power feed circuit also operates to sink a shunt current when power harvested from the receiver circuit is more than is needed to power the components in the transmitter circuit.

Abstract translation: 功率收集电路包括新的发射机拓扑结构，其确保形成功率收集电路的薄氧化物晶体管的结不会经受超过最大可容忍结电压的晶体管结的电压。 补充供电电路用于在从接收器电路收集的功率不足以对发射机电路的这些组件充分供电时，向发射机电路中的组件提供补充馈电电流，这可能在耦合发射机的通信信道的高频操作期间发生 和接收器电路。 当从接收器电路收集的功率大于为发射机电路中的组件供电所需的功率时，辅助馈电电路还用于吸收分流电流。

公开(公告)号：US20140292402A1

公开(公告)日：2014-10-02

申请号：US14231133

申请日：2014-03-31

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Tapas NANDY ,  Anchal JAIN

IPC: H03K9/08

CPC classification number: H03K9/08

Abstract: A PWM receiver circuit receives and demodulates pulse width modulated (PWM) data signals without requiring synchronization such that no synchronization preamble need be provided with the PWM data signal. Embodiments may consume less power since there is no need to repeatedly synchronize a PLL, counter or other circuitry to the PWM data signal. Furthermore, the PWM receiver circuit operates in view of or is “tolerant” to jitter in the frequency of the PWM signal and also to a relatively wide range of intentional variation in the frequency. Interleaved operation of parallel PWM receiver circuits are utilized in some embodiments. In one embodiment currents are integrated during low and high portions of the duty cycle of the PWM data signal and the difference in the respective voltages generated through such integration used to demodulate the PWM data signal.

Abstract translation: PWM接收器电路接收和解调脉宽调制（PWM）数据信号而不需要同步，使得不需要向PWM数据信号提供同步前同步码。 实施例可以消耗更少的功率，因为​​不需要将PLL，计数器或其他电路重复同步到PWM数据信号。 此外，PWM接收器电路在PWM信号的频率中考虑到或者“容忍”抖动以及频率的有意变化的相对宽的范围。 在一些实施例中，采用并行PWM接收器电路的交织操作。 在一个实施例中，在PWM数据信号的占空比的低和高部分集成电流，并且通过这样的积分产生的各个电压的差用于解调PWM数据信号。