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    INTEGRATED CIRCUIT INCLUDING A PHYSICALLY UNCLONABLE FUNCTION DEVICE AND CORRESPONDING METHOD FOR IMPLEMENTING A PHYSICALLY UNCLONABLE FUNCTION
    3.
    发明申请
    INTEGRATED CIRCUIT INCLUDING A PHYSICALLY UNCLONABLE FUNCTION DEVICE AND CORRESPONDING METHOD FOR IMPLEMENTING A PHYSICALLY UNCLONABLE FUNCTION 有权

    公开(公告)号：US20250111876A1

    公开(公告)日：2025-04-03

    申请号：US18978540

    申请日：2024-12-12

    Applicant: STMICROELECTRONICS S.r.l. ,  STMICROELECTRONICS (ROUSSET) SAS

    Inventor： Antonino CONTE ,  Francesco LA ROSA

    IPC: G11C13/00 ,  H01L23/00

    Abstract: Unclonable function circuitry includes a plurality of pairs of phase-change memory cells in a virgin state, and sensing circuitry coupled to the plurality of pairs of phase-change memory cells in the virgin state. The sensing circuitry identifies a subset of the plurality of pairs of phase-change memory cells in the virgin state based on a reliability mask. Signs of differences of effective resistance values of the identified subset of the plurality of pairs of phase-change memory cells in the virgin state are sensed by the sensing circuitry. The sensing circuitry generates a string of bits based on the sensed signs of differences in the effective resistance values of the identified subset of the plurality of pairs of phase-change memory cells in the virgin state. Processing circuitry coupled to the unclonable function circuitry, in operation, executes one or more operations using the generated string of bits.

    DECODING ARCHITECTURE AND METHOD FOR PHASE CHANGE NON-VOLATILE MEMORY DEVICES
    4.
    发明申请
    DECODING ARCHITECTURE AND METHOD FOR PHASE CHANGE NON-VOLATILE MEMORY DEVICES 有权
    解码结构和相位改变非易失性存储器件的方法

    公开(公告)号：US20130258766A1

    公开(公告)日：2013-10-03

    申请号：US13780280

    申请日：2013-02-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Antonino CONTE ,  Francesca GRANDE ,  Alberto Jose' DIMARTINO ,  Alfredo SIGNORELLO

    IPC: G11C13/00

    CPC classification number: G11C13/0009 ,  G11C5/146 ,  G11C7/12 ,  G11C8/10 ,  G11C8/12 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C2207/005

    Abstract: A decoding system for a phase change non-volatile memory device having a memory array may include a column decoder that selects at least one column of the memory array during programming operations. The decoding system includes a selection circuit that includes selection switches on a number of hierarchical decoding levels for defining a conductive path between at least one column and a driving stage. A biasing circuit may supply biasing signals to the selection switches for defining the first conductive path and bringing the selected column to a programming voltage value. The programming selection circuit may have protection elements between columns and the selection switches. The selection switches and the protection elements may include metal oxide semiconductor (MOS) transistors having an upper threshold voltage level lower than the programming voltage.

    Abstract translation: 具有存储器阵列的相变非易失性存储器件的解码系统可以包括在编程操作期间选择存储器阵列的至少一列的列解码器。 解码系统包括选择电路，其包括用于限定至少一个列和驱动级之间的导电路径的多个分层解码级别的选择开关。 偏置电路可以向选择开关提供偏置信号，用于限定第一导电路径并使所选列进入编程电压值。 编程选择电路可以具有列和选择开关之间的保护元件。 选择开关和保护元件可以包括具有比编程电压低的上阈值电压电平的金属氧化物半导体（MOS）晶体管。

    HIGH THROUGHPUT PROGRAMMING SYSTEM AND METHOD FOR A PHASE CHANGE NON-VOLATILE MEMORY DEVICE
    5.
    发明申请
    HIGH THROUGHPUT PROGRAMMING SYSTEM AND METHOD FOR A PHASE CHANGE NON-VOLATILE MEMORY DEVICE 有权
    相位改变非易失性存储器件的高通量编程系统和方法

    公开(公告)号：US20150243356A1

    公开(公告)日：2015-08-27

    申请号：US14623300

    申请日：2015-02-16

    Applicant: STMICROELECTRONICS S.r.l. ,  STMICROELECTRONICS PTE LTD

    Inventor： Antonino CONTE ,  Alberto Jose' DI MARTINO ,  Kailash KHAIRNAR

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C8/04 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0061 ,  G11C13/0097 ,  G11C2213/79

    Abstract: A phase change non-volatile memory device has a memory array with a plurality of memory cells arranged in rows and columns, a column decoder and a row decoder designed to select columns, and, respectively, rows of the memory array during operations of programming of corresponding memory cells. A control logic, coupled to the column decoder and the row decoder, is designed to execute a sequential programming command, to control the column decoder and row decoder to select one column of the memory array and execute sequential programming operations on a desired block of memory cells belonging to contiguous selected rows of the selected column.

    Abstract translation: 相变非易失性存储器件具有存储器阵列，其具有排列成行和列的多个存储器单元，列解码器和行解码器，被设计为在编程操作期间选择列以及分别存储器阵列的行 相应的存储单元。 耦合到列解码器和行解码器的控制逻辑被设计为执行顺序编程命令，以控制列解码器和行解码器来选择存储器阵列的一列并对期望的存储块执行顺序编程操作 属于所选列的连续选定行的单元格。

    VOLTAGE REGULATOR FOR CONTACT-LESS ELECTRONIC DEVICES
    6.
    发明申请
    VOLTAGE REGULATOR FOR CONTACT-LESS ELECTRONIC DEVICES 有权
    用于不连接电子设备的电压调节器

    公开(公告)号：US20130221938A1

    公开(公告)日：2013-08-29

    申请号：US13770047

    申请日：2013-02-19

    Applicant: STMicroelectronics S.r.l.

    Inventor： Antonino CONTE ,  Carmelo Ucciardello ,  Gianbattista Logiudice

    IPC: G05F1/10

    CPC classification number: G05F1/10 ,  G06K19/0713 ,  G06K19/0715 ,  H02M3/07 ,  H02M3/1584

    Abstract: A voltage regulator has an input terminal for receiving a supply voltage and an output terminal for providing a regulated voltage and a regulated current. Furthermore, the voltage regulator includes a regulator for generating the regulated voltage and the regulated current according to a regulation of the supply voltage. The regulator includes a plurality of regulation branches arranged between the input terminal and the output terminal, each one for providing an output voltage used for obtaining the regulated voltage and for providing an output current contributing to define the regulated current. The regulation branches are partitioned into a plurality of subsets each one including components adapted to operate within a corresponding maximum voltage different from the maximum voltage of the other subsets. In addition, the regulator includes a selector for selectively enabling the regulation branches according to an indicator of the supply voltage.

    Abstract translation: 电压调节器具有用于接收电源电压的输入端子和用于提供稳定电压和调节电流的输出端子。 此外，电压调节器包括用于根据电源电压的调节产生调节电压和调节电流的调节器。 调节器包括布置在输入端子和输出端子之间的多个调节分支，每个调节分支用于提供用于获得调节电压的输出电压并且用于提供有助于限定调节电流的输出电流。 调节分支被划分成多个子集，每个子​​集包括适于在不同于其他子集的最大电压的对应最大电压内操作的组件。 此外，调节器包括一个选择器，用于根据电源电压的指示器选择性地启用调节分支。

    ERROR CORRECTION IN MEMORY DEVICES BY MULTIPLE READINGS WITH DIFFERENT REFERENCES
    7.
    发明申请
    ERROR CORRECTION IN MEMORY DEVICES BY MULTIPLE READINGS WITH DIFFERENT REFERENCES 有权
    不同参考文献的多篇阅读记忆体设备中的错误校正

    公开(公告)号：US20150212881A1

    公开(公告)日：2015-07-30

    申请号：US14597845

    申请日：2015-01-15

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Pte Ltd

    Inventor： Antonino CONTE ,  Kailash KHAIRNAR

    IPC: G06F11/10 ,  G11C29/52

    CPC classification number: G06F11/1068 ,  G06F11/08 ,  G06F11/1048 ,  G11C13/0004 ,  G11C13/004 ,  G11C29/52 ,  G11C2013/0054

    Abstract: A memory device may include memory cells. The method may include receiving a request of reading a selected data word associated with a selected code word stored with an error correction code, and reading a first code word representing a first version of the selected code word by comparing a state of each selected memory cell with a first reference. The method may include verifying the first code word, setting the selected code word according to the first code word in response to a positive verification, reading at least one second code word representing a second version of the selected code word, verifying the second code word, and setting the selected code word according to the second code word in response to a negative verification of the first code word and to a positive verification of the second code word.

    Abstract translation: 存储器件可以包括存储器单元。 该方法可以包括：接收读取与通过纠错码存储的所选码字相关联的所选择的数据字的请求，以及通过比较所选择的存储单元的状态来读取表示所选码字的第一版本的第一代码字 第一个参考。 该方法可以包括验证第一代码字，响应于正验证，根据第一代码字设置所选择的代码字，读取表示所选代码字的第二版本的至少一个第二代码字，验证第二代码字 并且响应于第一代码字的否定验证和第二代码字的肯定验证，根据第二代码字设置所选择的代码字。

    HIGH-EFFICIENCY DRIVING STAGE FOR PHASE CHANGE NON-VOLATILE MEMORY DEVICES
    8.
    发明申请
    HIGH-EFFICIENCY DRIVING STAGE FOR PHASE CHANGE NON-VOLATILE MEMORY DEVICES 有权
    相位改变非易失性存储器件的高效驱动级

    公开(公告)号：US20130229863A1

    公开(公告)日：2013-09-05

    申请号：US13771663

    申请日：2013-02-20

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： Antonino CONTE ,  Maria GIAQUINTA ,  Loredana CHIARAMONTE

    IPC: G11C13/00

    CPC classification number: G11C13/0004 ,  G11C5/145 ,  G11C5/147 ,  G11C13/0038 ,  G11C13/0069

    Abstract: A driving stage for a phase change non-volatile memory device may have an output driving unit which supplies an output driving current during an operation of programming of at least one memory cell. A driving-control unit receives an input current and generates at output a first control signal that controls supply of the output driving current by the output driving unit in such a way that a value of this current has a desired relation with the input current. A level-shifter element, set between the output of the driving-control unit and a control input of the output driving unit, determines a level shift of the voltage of the first control signal so as to supply to the control input of the output driving unit a second control signal, having a voltage value that is increased with respect to, and is a function of, the first control signal.

    Abstract translation: 用于相变非易失性存储器件的驱动级可以具有输出驱动单元，其在至少一个存储器单元的编程操作期间提供输出驱动电流。 驱动控制单元接收输入电流并在输出端产生控制由输出驱动单元输出驱动电流的供给的第一控制信号，使得该电流的值与输入电流具有期望的关系。 设置在驱动控制单元的输出和输出驱动单元的控制输入之间的电平移动元件确定第一控制信号的电压的电平偏移，以便提供给输出驱动的控制输入 单元具有第二控制信号，具有相对于第一控制信号而增加并且是第一控制信号的函数的电压值。

    LOW DROP-OUT REGULATOR CIRCUIT, CORRESPONDING DEVICE AND METHOD
    9.
    发明公开
    LOW DROP-OUT REGULATOR CIRCUIT, CORRESPONDING DEVICE AND METHOD 审中-公开

    公开(公告)号：US20230333583A1

    公开(公告)日：2023-10-19

    申请号：US18295774

    申请日：2023-04-04

    Applicant: STMICROELECTRONICS S.r.l.

    Inventor： Antonino CONTE ,  Marco RUTA ,  Francesco TOMAIUOLO ,  Michelangelo PISASALE ,  Marion Helne GRIMAL

    IPC: G05F1/59 ,  G05F1/575

    CPC classification number: G05F1/59 ,  G05F1/575

    Abstract: A LDO regulator circuit comprises an input comparator and driver circuitry including transistors having a current flow path therethrough coupled to an output node of the regulator. First and second driver each comprises: driver transistors having the current flow paths therethrough coupled to the output node, capacitive boost circuitry that applies to the drive transistors a voltage-pumped replica of the comparison signal. Voltage refresh transistor circuitry coupled to the capacitive boost circuitry transfer thereon the voltage-pumped replica. The first and second drivers can be controllably switched between a first mode of operation, during which the current flow path through the driver transistors is conductive or non-conductive based on the voltage-pumped replica of the comparison signal, and a second mode, during which the voltage refresh transistor circuitry is activated to transfer the voltage-pumped replica of the comparison signal, and the current flow path through the driver transistors is non-conductive.

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