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    Current steering digital to analog converter with decoder free quad switching
    1.
    发明授权
    Current steering digital to analog converter with decoder free quad switching 有权

    公开(公告)号：US10148277B1

    公开(公告)日：2018-12-04

    申请号：US15600152

    申请日：2017-05-19

    Applicant: STMicroelectronics International N.V.

    Inventor： Pratap Narayan Singh ,  Vivek Tripathi ,  Anil Kumar ,  Rakesh Malik

    IPC: H03M1/08 ,  H03M1/66 ,  H03M1/74 ,  H03M1/06

    Abstract: Disclosed herein is a digital to analog converter including a first dynamic latch receiving a data signal and an inverse of the data signal. The first dynamic latch is clocked by a clock signal and configured to generate first and second quad switching control signals as a function of the data signal and the inverse of the data signal. A second dynamic latch receives the data signal and the inverse of the data signal, is clocked by an inverse of the clock signal, and is configured to generate third and fourth quad switching control signals as a function of the data signal and the inverse of the data signal. A quad switching bit cell is configured to generate an analog representation of the data signal as a function of the first, second, third, and fourth quad switching signals.

    Adaptive delay based asynchronous successive approximation analog-to-digital converter
    4.
    发明授权
    Adaptive delay based asynchronous successive approximation analog-to-digital converter 有权
    基于自适应延迟的异步逐次逼近模数转换器

    公开(公告)号：US09300317B2

    公开(公告)日：2016-03-29

    申请号：US14930708

    申请日：2015-11-03

    Applicant: STMicroelectronics International N.V.

    Inventor： Rakesh Malik ,  Chandrajit Debnath ,  Ashish Sharma Kumar ,  Pratap Narayan Singh

    IPC: H03M1/34 ,  H03M1/12 ,  H03M1/06 ,  H03M1/46 ,  H03M1/00

    CPC classification number: H03M1/125 ,  H03M1/00 ,  H03M1/0612 ,  H03M1/069 ,  H03M1/0695 ,  H03M1/12 ,  H03M1/46 ,  H03M1/462

    Abstract: An asynchronous SAR ADC converts an analog signal into a series of digital pulses in an efficient, low power manner. In synchronous SAR ADC circuits, a separate and cumbersome clock signal is used to trigger the internal circuitry of the SAR ADC. Instead of triggering the components of the SAR DAC synchronously with a clock signal, the asynchronous solution uses its own internal signals to trigger its components in an asynchronous cyclic manner. Further, in order to increase efficiency and guard against circuit failures due to difficulties arising from transient signals, the asynchronous SAR ADC may also include a delay circuit for introducing a variable delay to the SAR ADC cycle.

    Abstract translation: 异步SAR ADC以有效，低功耗的方式将模拟信号转换为一系列数字脉冲。 在同步SAR ADC电路中，单独和繁琐的时钟信号用于触发SAR ADC的内部电路。 异步解决方案不是以时钟信号同步触发SAR DAC的组件，而是以其自身的内部信号以异步循环方式触发其组件。 此外，为了提高效率并防止由于瞬态信号引起的困难而导致的电路故障，异步SAR ADC还可以包括用于将可变延迟引入SAR ADC周期的延迟电路。

    Reference voltage generation circuit
    7.
    发明授权
    Reference voltage generation circuit 有权
    参考电压发生电路

    公开(公告)号：US09588538B2

    公开(公告)日：2017-03-07

    申请号：US14675309

    申请日：2015-03-31

    Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

    Inventor： Jean-Pierre Blanc ,  Pratap Narayan Singh

    IPC: H05F3/02 ,  G05F3/16 ,  G05F3/26 ,  G05F3/30

    CPC classification number: G05F3/16 ,  G05F3/26 ,  G05F3/267 ,  G05F3/30

    Abstract: A reference voltage generation circuit, including a first current source in series with a first bipolar transistor; a second current source in series with a first resistor; a third current source in series with a second bipolar transistor, the third current source being assembled as a current mirror with the first current source; a second resistor between the base of the second bipolar transistor and the junction point between the current source and the first resistor; and a fourth current source in series with a third resistor, the junction point between the fourth current source and the third resistor defining a reference voltage terminal.

    Abstract translation: 参考电压产生电路，包括与第一双极晶体管串联的第一电流源; 与第一电阻器串联的第二电流源; 与第二双极晶体管串联的第三电流源，所述第三电流源被组装为具有所述第一电流源的电流镜; 第二电阻器，位于第二双极晶体管的基极与电流源与第一电阻之间的连接点之间; 以及与第三电阻器串联的第四电流源，所述第四电流源和所述第三电阻器之间的连接点限定参考电压端子。

    Variable delay element
    8.
    发明授权
    Variable delay element 有权
    可变延迟元件

    公开(公告)号：US09432008B2

    公开(公告)日：2016-08-30

    申请号：US14337896

    申请日：2014-07-22

    Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

    Inventor： Stéphane Le Tual ,  Pratap Narayan Singh

    IPC: H03K5/13 ,  H03K5/134 ,  H03K5/00

    CPC classification number: H03K5/134 ,  H03K5/13 ,  H03K2005/00032 ,  H03K2005/00208 ,  H03K2005/00215 ,  H03K2217/0018

    Abstract: A delay circuit includes first and second transistors and a biasing circuit. The first transistor has a control node coupled to an input node of the delay circuit, a first main current node coupled to a first supply voltage, and a second main current node coupled to an output node of the delay circuit. A second transistor has a control node coupled to the input node, a first main current node coupled to a second supply voltage, and a second main current node coupled to the output node. The biasing circuit is configured to generate first and second differential control voltages, to apply the first differential control voltage to a further control node of the first transistor and to apply the second differential control voltage to a further control node of the second transistor.

    Abstract translation: 延迟电路包括第一和第二晶体管和偏置电路。 第一晶体管具有耦合到延迟电路的输入节点的控制节点，耦合到第一电源电压的第一主电流节点和耦合到延迟电路的输出节点的第二主电流节点。 第二晶体管具有耦合到输入节点的控制节点，耦合到第二电源电压的第一主电流节点和耦合到输出节点的第二主电流节点。 偏置电路被配置为产生第一和第二差分控制电压，以将第一差分控制电压施加到第一晶体管的另一控制节点，并将第二差分控制电压施加到第二晶体管的另一个控制节点。

    Supply voltage compensation for an input/output driver circuit using clock signal frequency comparison
    9.
    发明授权
    Supply voltage compensation for an input/output driver circuit using clock signal frequency comparison 有权

    公开(公告)号：US10608637B2

    公开(公告)日：2020-03-31

    申请号：US15698022

    申请日：2017-09-07

    Applicant: STMicroelectronics International N.V.

    Inventor： Prashant Singh ,  Pratap Narayan Singh

    IPC: H03K5/22 ,  H03K5/153 ,  H03K19/003 ,  H03K17/14 ,  H03K19/1778

    Abstract: A process and temperature variation operating condition that is globally applicable to an integrated circuit die is sensed in a core circuit region to generate a global process and temperature compensation signal. A voltage variation operating condition that is locally applicable to an input/output circuit within a peripheral circuit region of the integrated circuit die is sensed to generate a local voltage compensation signal. More specifically, the localized voltage operating condition is generated as a function of a measured difference in frequency between a first clock signal generated in the peripheral circuit region in response to a supply voltage subject to voltage variation and a second clock signal generated in the core circuit region in response to a fixed bandgap reference voltage. The operation of the input/output circuit is then altered in response to the global process and temperature compensation signal and in response to the local voltage compensation signal.

    Circuit and method for signal conversion
    10.
    发明授权
    Circuit and method for signal conversion 有权
    电路和信号转换方法

    公开(公告)号：US09000964B2

    公开(公告)日：2015-04-07

    申请号：US14294300

    申请日：2014-06-03

    Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

    Inventor： Stéphane Le Tual ,  Pratap Narayan Singh

    IPC: H03M1/00 ,  H03M1/08 ,  H03K3/013 ,  G11C27/02 ,  H03K19/0185

    CPC classification number: H03M1/08 ,  G11C27/024 ,  G11C27/026 ,  H03K3/013 ,  H03K19/018528

    Abstract: The invention concerns a circuit comprising: a first transistor (202) having a first main current node coupled to a first voltage signal (CNVDD), a control node coupled to a second voltage signal (CPVDD) and a second main current node coupled to an output node (206) of the circuit; a second transistor (204) having a first main current node coupled to a third voltage signal (CNGND), a control node coupled to a fourth voltage signal (CPGND) and a second main current node coupled to said output node of the circuit; and circuitry (210, 212) adapted to generate said first, second, third and fourth voltage signals based on a pair of differential input signals (CP, CN), wherein said first and second voltage signals are both referenced to a first supply voltage (VDD) and wherein said third and fourth voltage signals are both referenced to a second supply voltage (GND).

    Abstract translation: 本发明涉及一种电路，包括：具有耦合到第一电压信号（CNVDD）的第一主电流节点的第一晶体管（202），耦合到第二电压信号（CPVDD）的控制节点和耦合到第一电流信号 输出节点（206）; 第二晶体管（204），其具有耦合到第三电压信号（CNGND）的第一主电流节点，耦合到第四电压信号（CPGND）的控制节点和耦合到所述电路的所述输出节点的第二主电流节点; 以及适于基于一对差分输入信号（CP，CN）产生所述第一，第二，第三和第四电压信号的电路（210,212），其中所述第一和第二电压信号都参考第一电源电压 VDD），并且其中所述第三和第四电压信号都参考第二电源电压（GND）。

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