公开(公告)号：US09762243B2

公开(公告)日：2017-09-12

申请号：US14989052

申请日：2016-01-06

Applicant: STMicroelectronics International N.V

Inventor： Vinod Kumar ,  Saiyid Mohammad Irshad Rizvi

IPC: H03K19/01 ,  H03K19/00 ,  H03K19/0175 ,  G06F1/32

CPC classification number: H03K19/017545 ,  G06F1/329 ,  H03K19/0008 ,  Y02D10/24 ,  Y10T307/406

Abstract: An apparatus includes a first input/output (I/O) interface circuit having a maximum voltage rating. The first I/O interface circuit includes a level shifter and an output stage. A reference voltage bias generator is coupled to the first I/O interface circuit, to a first supply voltage, and to a first ground potential. The reference voltage bias generator is configured to generate a plurality of reference bias signals, including a first reference voltage and a second reference voltage. When the first supply voltage is not greater than the maximum voltage rating, the first reference voltage is equal to the first supply voltage and the second reference voltage is equal to the first ground potential. When the first supply voltage is greater than the maximum voltage rating, the first reference voltage is equal to the first supply voltage times a first fraction, and the second reference voltage is equal to the first supply voltage times a second fraction.

公开(公告)号：US09264045B2

公开(公告)日：2016-02-16

申请号：US14231939

申请日：2014-04-01

Applicant: STMicroelectronics International N.V.

Inventor： Sameer Vashishtha ,  Saiyid Mohammad Irshad Rizvi

IPC: H03K5/08 ,  H03K19/0948 ,  H03K19/003 ,  H03K19/0185 ,  H03K19/00

CPC classification number: H03K19/09487 ,  H03K19/0027 ,  H03K19/00361 ,  H03K19/018521

Abstract: A buffer includes an input configured to receive a first digital signal having first and second logic states referenced, respectively, to a first high voltage and a first low voltage of a first supply domain. A first inverter circuit includes a pMOS transistor and nMOS transistor having gate terminals connected to the input. A second inverter is connected in series with the output of the first inverter. The second inverter has an output configured to generate a second digital signal having first and second logic states referenced, respectively, to a second high voltage and a second low voltage of a second, different, supply domain, wherein at least the second high voltage is greater than the first high voltage. A feedback circuit is configured to apply the second digital signal as a bias to a transistor body of the p-MOS transistor of the first inverter circuit.

Abstract translation: 缓冲器包括被配置为接收具有分别被引用到第一供电域的第一高电压和第一低电压的第一和第二逻辑状态的第一数字信号的输入。 第一反相器电路包括具有连接到输入的栅极端子的pMOS晶体管和nMOS晶体管。 第二反相器与第一反相器的输出串联。 第二反相器具有被配置为产生具有第一和第二逻辑状态的第二数字信号的第二数字信号，第一和第二逻辑状态分别被称为第二高电压和第二不同供电域的第二低电压，其中至少第二高电压是 大于第一高电压。 反馈电路被配置为将第二数字信号作为偏置施加到第一反相器电路的p-MOS晶体管的晶体管本体。

公开(公告)号：US09467125B2

公开(公告)日：2016-10-11

申请号：US14573129

申请日：2014-12-17

Applicant: STMicroelectronics International N.V.

Inventor： Vinod Kumar ,  Saiyid Mohammad Irshad Rizvi

IPC: H03K3/3565

CPC classification number: H03K3/3565

Abstract: The Schmitt trigger circuit includes a signal input, a first inverter coupled to the signal input and configured to operate at a first voltage, and a second inverter coupled downstream of the first inverter and configured to operate at a second voltage lower than the first voltage. A protection device is coupled between the first inverter and the second inverter, and configured to limit a voltage input to the second inverter at the second voltage. A feedback circuit is coupled downstream of the protection device between the first inverter and the second inverter and configured to introduce hysteresis. An output circuit is coupled to the second inverter and configured to provide an output signal at the second voltage. The approach provides an architecture for 3.3V receivers designed by using 1.8V devices, without active power consumption from the I/O PAD during transition, and/or that supports CMOS standard levels for 1.8V and 3.3V receivers.

Abstract translation: 施密特触发电路包括信号输入端，耦合到信号输入并被配置为以第一电压工作的第一反相器，以及耦合在第一反相器下游的第二反相器，并被配置为在低于第一电压的第二电压下工作。 保护装置耦合在第一反相器和第二反相器之间，并且被配置为将第二反相器的电压输入限制在第二电压。 反馈电路被耦合在第一逆变器和第二逆变器之间的保护装置的下游，并被配置为引入滞后。 输出电路耦合到第二反相器并且被配置为提供处于第二电压的输出信号。 该方法为通过使用1.8V器件设计的3.3V接收器提供了架构，在转换期间没有来自I / O PAD的有功功耗，和/或支持1.8V和3.3V接收器的CMOS标准电平。

公开(公告)号：US11923855B2

公开(公告)日：2024-03-05

申请号：US17931864

申请日：2022-09-13

Applicant: STMicroelectronics International N.V.

Inventor： Manoj Kumar Tiwari ,  Saiyid Mohammad Irshad Rizvi

IPC: H03K3/00 ,  H03K3/037 ,  H03K3/13

CPC classification number: H03K3/0377 ,  H03K3/037 ,  H03K3/13

Abstract: An integrated circuit includes an input pad and a Schmitt trigger coupled to the input pad. The Schmitt trigger includes a first inverter and a second inverter. The Schmitt trigger includes a pull-up transistor coupled to an input of the second inverter and configure to supply a high reference voltage to the input of the second inverter.

公开(公告)号：US11522521B2

公开(公告)日：2022-12-06

申请号：US17223963

申请日：2021-04-06

Applicant: STMicroelectronics International N.V.

Inventor： Manoj Kumar Tiwari ,  Saiyid Mohammad Irshad Rizvi

IPC: H03H11/04 ,  H03H19/00 ,  G06F1/10

Abstract: A glitch filter is provided. The glitch filter receives an input signal and sets a voltage level of an intermediary input node in accordance with a state of the input signal. The glitch filter charges or discharges a switched capacitance based on the voltage level of the intermediary input node and charges or discharges a filter capacitance based on a charge of the switched capacitance. The glitch filter sets a state of an output signal based on the charge of the filter capacitance. The glitch filter includes a reset stage that at least partially filters a burst of glitches in the input signal from the output signal by controlling the charge of the switched capacitance based on the state of the input signal and the state of the output signal.

公开(公告)号：US09473135B2

公开(公告)日：2016-10-18

申请号：US14500076

申请日：2014-09-29

Applicant: STMicroelectronics International N.V.

Inventor： Paras Garg ,  Rajesh Yadav ,  Saiyid Mohammad Irshad Rizvi ,  Ravinder Kumar

IPC: H03K3/00 ,  H03K17/687 ,  H03K19/0185

CPC classification number: H03K17/687 ,  H03K19/0185 ,  H03K2217/0018

Abstract: A drive circuit includes a first drive transistor coupled between a first supply node and an output pad of an integrated circuit and a second drive transistor coupled between a second supply node and the output pad. The first drive transistor and second drive transistors are controlled by a control signal. A body bias generator circuit is configured to apply a variable first body bias to the first transistor and a variable second body bias to the second transistor. The variable first and second body biases are generated as a function of the control signal and a voltage at the output pad.

Abstract translation: 驱动电路包括耦合在集成电路的第一电源节点和输出焊盘之间的第一驱动晶体管，以及耦合在第二电源节点和输出焊盘之间的第二驱动晶体管。 第一驱动晶体管和第二驱动晶体管由控制信号控制。 体偏置发生器电路被配置为将可变第一体偏置施加到第一晶体管，并将可变第二体偏置施加到第二晶体管。 可变的第一和第二体偏置作为控制信号和输出焊盘处的电压的函数产生。

公开(公告)号：US20160118986A1

公开(公告)日：2016-04-28

申请号：US14989052

申请日：2016-01-06

Applicant: STMicroelectronics International N.V

Inventor： Vinod Kumar ,  Saiyid Mohammad Irshad Rizvi

IPC: H03K19/0175 ,  H03K19/00

CPC classification number: H03K19/017545 ,  G06F1/329 ,  H03K19/0008 ,  Y02D10/24 ,  Y10T307/406

Abstract: An apparatus includes a first input/output (I/O) interface circuit having a maximum voltage rating. The first I/O interface circuit includes a level shifter and an output stage. A reference voltage bias generator is coupled to the first I/O interface circuit, to a first supply voltage, and to a first ground potential. The reference voltage bias generator is configured to generate a plurality of reference bias signals, including a first reference voltage and a second reference voltage. When the first supply voltage is not greater than the maximum voltage rating, the first reference voltage is equal to the first supply voltage and the second reference voltage is equal to the first ground potential. When the first supply voltage is greater than the maximum voltage rating, the first reference voltage is equal to the first supply voltage times a first fraction, and the second reference voltage is equal to the first supply voltage times a second fraction.

Abstract translation: 一种装置包括具有最大额定电压的第一输入/输出（I / O）接口电路。 第一I / O接口电路包括电平转换器和输出级。 参考电压偏置发生器耦合到第一I / O接口电路，耦合到第一电源电压和第一接地电位。 参考电压偏置发生器被配置为产生包括第一参考电压和第二参考电压的多个参考偏置信号。 当第一电源电压不大于最大额定电压时，第一参考电压等于第一电源电压，第二参考电压等于第一地电位。 当第一电源电压大于最大额定电压时，第一参考电压等于第一电源电压乘以第一分数，第二参考电压等于第一电源电压乘以第二分数。

公开(公告)号：US20150280716A1

公开(公告)日：2015-10-01

申请号：US14231939

申请日：2014-04-01

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Sameer Vashishtha ,  Saiyid Mohammad Irshad Rizvi

IPC: H03K19/0948 ,  H03K19/0185 ,  H03K19/00 ,  H03K19/003

CPC classification number: H03K19/09487 ,  H03K19/0027 ,  H03K19/00361 ,  H03K19/018521

Abstract: A buffer includes an input configured to receive a first digital signal having first and second logic states referenced, respectively, to a first high voltage and a first low voltage of a first supply domain. A first inverter circuit includes a pMOS transistor and nMOS transistor having gate terminals connected to the input. A second inverter is connected in series with the output of the first inverter. The second inverter has an output configured to generate a second digital signal having first and second logic states referenced, respectively, to a second high voltage and a second low voltage of a second, different, supply domain, wherein at least the second high voltage is greater than the first high voltage. A feedback circuit is configured to apply the second digital signal as a bias to a transistor body of the p-MOS transistor of the first inverter circuit.

Abstract translation: 缓冲器包括被配置为接收具有分别被引用到第一供电域的第一高电压和第一低电压的第一和第二逻辑状态的第一数字信号的输入。 第一反相器电路包括具有连接到输入的栅极端子的pMOS晶体管和nMOS晶体管。 第二反相器与第一反相器的输出串联。 第二反相器具有被配置为产生具有第一和第二逻辑状态的第二数字信号的第二数字信号，第一和第二逻辑状态分别被称为第二高电压和第二不同供电域的第二低电压，其中至少第二高电压是 大于第一高电压。 反馈电路被配置为将第二数字信号作为偏置施加到第一反相器电路的p-MOS晶体管的晶体管本体。

公开(公告)号：US08981817B2

公开(公告)日：2015-03-17

申请号：US13926748

申请日：2013-06-25

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Vinod Kumar ,  Pradeep Kumar Badrathwal ,  Saiyid Mohammad Irshad Rizvi ,  Paras Garg ,  Kallol Chatterjee ,  Pierre Dautriche

IPC: H03K3/00

CPC classification number: H03K19/00384

Abstract: A circuit having a centralized PT compensation circuit to provide compensation signals to localized I/O blocks on the chip. Process variations and temperature variations tend to be approximately uniform across an integrated circuit chip. Thus, a single, centralized PT compensation circuit may be used instead of one PT compensation circuit per I/O section as with solutions of the past. Further, the PT compensation circuit may generate a digital code indicative of the effects of process and temperature. Further yet, each section of I/O block may have a local voltage compensation circuit to compensate the voltage variation of the I/O block. The voltage compensation circuit utilizes an independent reference voltage. The reference voltage is generated by the PT compensation circuit, which is placed centrally in the IC chip and hence any need to repeat the reference generation for each I/O block is eliminated.

Abstract translation: 具有集中PT补偿电路以向芯片上的局部I / O块提供补偿信号的电路。 整个集成电路芯片的工艺变化和温度变化趋向于大致均匀。 因此，与过去的解决方案一样，可以使用单个集中式PT补偿电路来代替每个I / O部分的一个PT补偿电路。 此外，PT补偿电路可以产生指示过程和温度的影响的数字代码。 此外，I / O块的每个部分可以具有用于补偿I / O块的电压变化的局部电压补偿电路。 电压补偿电路采用独立的参考电压。 参考电压由放置在IC芯片中央的PT补偿电路产生，因此不需要重复每个I / O块的参考生成。

公开(公告)号：US11075624B2

公开(公告)日：2021-07-27

申请号：US16906664

申请日：2020-06-19

Applicant: STMicroelectronics International N.V.

Inventor： Saiyid Mohammad Irshad Rizvi ,  Manish Garg

IPC: H03K19/0185 ,  H03K17/16 ,  H03K19/20 ,  H03K19/0175

Abstract: A hybrid driver receives complementary high-speed input data signals and a pair of low-speed input data signals and selects one of the pairs of input data signals and drives output data signals on first and second output nodes based on the selected pair of input data signals. The hybrid driver includes first and second driver circuits coupled to the first and second output nodes, respectively. Each driver circuit includes first and second series-connected transistors coupled between a first supply voltage node and a reference voltage node, with an interconnection of the first and second series-connected transistors coupled to the corresponding first or second output node. Each first and second driver circuit includes a third transistor coupled in parallel with the corresponding first transistor. Each first and third transistor couples in parallel the corresponding output node to a second supply voltage node responsive to the corresponding low-speed input data signal.