公开(公告)号：US20040151023A1

公开(公告)日：2004-08-05

申请号：US10715883

申请日：2003-11-18

Applicant: STMicroelectronics S.r.I. ,  OVONYX Inc.

Inventor： Osama Khouri ,  Ferdinando Bedeschi ,  Claudio Resta

IPC: G11C011/00

CPC classification number: G11C7/04 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2029/5002 ,  G11C2213/79

Abstract: A phase change memory includes a temperature sensor having a resistance variable with temperature with the same law as a phase-change storage element. The temperature sensor is formed by a resistor of chalcogenic material furnishing an electrical quantity that reproduces the relationship between the resistance of a phase change memory cell and temperature; the electrical quantity is processed so as to generate reference quantities as necessary for writing and reading the memory cells. The chalcogenic resistor has the same structure as a memory cell and is programmed with precision, preferably in the reset state.

Abstract translation: 相变存储器包括具有与相变存储元件相同定律的具有温度的电阻变化的温度传感器。 该温度传感器是由一个硫化物材料的电阻器形成的，它提供一个再现相变存储器单元电阻和温度之间的关系的电量; 对电量进行处理，以便产生写入和读取存储单元所需的参考量。 硫属电阻器具有与存储器单元相同的结构，并且精确地编程，优选地处于复位状态。

公开(公告)号：US20020191444A1

公开(公告)日：2002-12-19

申请号：US10119523

申请日：2002-04-09

Applicant: STMicroelectronics S.r.I.

Inventor： Stefano Gregori ,  Rino Micheloni ,  Andrea Pierin ,  Osama Khouri ,  Guido Torelli

IPC: G11C011/34

CPC classification number: G11C11/5628 ,  G11C16/12

Abstract: A method for programming a nonvolatile memory cell envisages applying in succession, to the gate terminal of the memory cell, a first and a second programming pulse trains with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next in the first programming pulse train is greater than the amplitude increment between one pulse and the next in the second programming pulse train. The programming method envisages applying, to the gate terminal of the memory cell and before the first programming pulse train, a third programming pulse train with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next may be less than the amplitude increment in the first programming pulse train and substantially equal to the amplitude increment in the second programming pulse train, or else may be greater than the amplitude increment in the first programming pulse train.

Abstract translation: 用于编程非易失性存储器单元的方法设想连续地应用到存储器单元的栅极端，第一和第二编程脉冲串，其阶梯形式的脉冲幅度增加，其中在一个脉冲和下一个脉冲之间的振幅增量 第一编程脉冲序列大于第二编程脉冲串中的一个脉冲和下一个脉冲之间的振幅增量。 编程方法设想在存储器单元的栅极端子和第一编程脉冲串之前施加具有阶梯式脉冲幅度增加的第三编程脉冲串，其中，一个脉冲与下一个脉冲之间的振幅增量可能小于 第一编程脉冲序列中的振幅增量基本上等于第二编程脉冲串中的幅度增量，或者可以大于第一编程脉冲序列中的振幅增量。

公开(公告)号：US20020089317A1

公开(公告)日：2002-07-11

申请号：US10008540

申请日：2001-11-07

Applicant: STMicroelectronics S.r.I.

Inventor： Osama Khouri ,  Ilaria Motta ,  Rino Micheloni ,  Guido Torelli

IPC: G05F001/40

CPC classification number: G05F1/56

Abstract: A voltage regulator having a comparator with an output terminal that is the output of the regulator, terminals for connection to a voltage supply, a source of a reference voltage connected to an input terminal of the comparator, and a feedback circuit connected between the output terminal and the other input terminal of the comparator. To prevent transients upon the transition from the standby state to the active state, there is provided a second reference-voltage source that provides a reference voltage substantially equal to that of the first source, a switch for connecting the second source to the other input terminal of the comparator, and a control circuit that can activate the supply of the regulator and can close the switch for a predetermined period of time when the supply of the regulator is activated.

Abstract translation: 一种电压调节器，具有比较器，输出端子是调节器的输出端子，用于连接到电压源的端子，连接到比较器的输入端子的参考电压源，以及连接在输出端子之间的反馈电路 和比较器的另一个输入端。 为了防止从待机状态转换到活动状态的瞬变，提供了提供基本上等于第一源的参考电压的第二参考电压源，用于将第二源连接到另一个输入端的开关 的控制电路，以及控制电路，其能够启动调节器的供应并且可以在调节器的供应被激活时将开关闭合预定的一段时间。

公开(公告)号：US20020048187A1

公开(公告)日：2002-04-25

申请号：US09972726

申请日：2001-10-04

Applicant: STMicroelectronics S.r.I.

Inventor： Andrea Pierin ,  Stefano Gregori ,  Rino Micheloni ,  Osama Khouri ,  Guido Torelli

IPC: G11C011/34

CPC classification number: G11C16/30 ,  G11C5/145 ,  G11C7/06 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/26

Abstract: A multilevel nonvolatile memory includes a supply line supplying a supply voltage, a voltage boosting circuit supplying a boosted voltage, higher than the supply voltage, a boosted line connected to the voltage boosting circuit and a reading circuit including at least one comparator. The comparator includes a first and a second input, a first and a second output, at least one amplification stage connected to the boosted line, and a boosted line latch stage connected to the supply line.

Abstract translation: 多级非易失性存储器包括提供电源电压的电源线，提供高于电源电压的升压电压的升压电路，连接到升压电路的升压线路和包括至少一个比较器的读取电路。 比较器包括第一和第二输入，第一和第二输出，连接到升压线路的至少一个放大级和连接到电源线的升压线路锁存级。

公开(公告)号：US20020057604A1

公开(公告)日：2002-05-16

申请号：US09953070

申请日：2001-09-13

Applicant: STMicroelectronics S.r.I.

Inventor： Osama Khouri ,  Alessandro Manstretta ,  Guido Torelli

IPC: G11C007/00

CPC classification number: G11C7/062 ,  G11C16/28 ,  G11C2207/063

Abstract: A reading circuit for semiconductor non-volatile memories connected to at least one selected cell and at least one reference cell, the circuit including current/voltage conversion circuits receiving at the input thereof a first current flowing through the selected cell and a second current flowing through the reference cell and providing respectively on a first circuit node a first selected cell voltage and on a second node a second reference cell voltage, as well as at least one differential amplifier, connected at the input of the first and the second nodes and having an output terminal effective to provide a logic signal correlated to the selected cell information. The reading circuit also includes at least a first voltage-controlled discharge switch circuit connected at the input of the first node and to a voltage reference, a second voltage-controlled discharge switch circuit connected at the input of the second node and to the voltage reference, as well as a first and a second voltage comparator circuits receiving at the input thereof the first selected cell voltage and the second reference cell voltage. Moreover, advantageously according to the invention, the comparator circuits are effective to control the switch circuits.

Abstract translation: 一种用于连接到至少一个选定单元和至少一个参考单元的半导体非易失性存储器的读取电路，所述电路包括电流/电压转换电路，其在输入端接收流过选定单元的第一电流和流过所选单元的第二电流 所述参考单元并且分别在第一电路节点上提供第一选择的单元电压，并在第二节点上提供第二参考单元电压以及至少一个差分放大器，所述差分放大器连接在所述第一和第二节点的输入端，并且具有 输出端有效地提供与所选择的单元信息相关的逻辑信号。 读取电路还包括至少连接在第一节点的输入端和电压基准的第一压控放电开关电路，连接在第二节点的输入端的第二压控放电开关电路和电压基准 以及在其输入端接收第一选定单元电压和第二参考单元电压的第一和第二电压比较器电路。 此外，有利地根据本发明，比较器电路有效地控制开关电路。

公开(公告)号：US20040228163A1

公开(公告)日：2004-11-18

申请号：US10782737

申请日：2004-02-18

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Osama Khouri ,  Claudio Resta

IPC: G11C011/00

CPC classification number: G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2213/79

Abstract: A phase change memory has an array formed by a plurality of cells, each including a memory element of calcogenic material and a selection element connected in series to the memory element; a plurality of address lines connected to the cells; a write stage and a reading stage connected to the array. The write stage is formed by current generators, which supply preset currents to the selected cells so as to modify the resistance of the memory element. Reading takes place in voltage, by appropriately biasing the selected cell and comparing the current flowing therein with a reference value.

Abstract translation: 相变存储器具有由多个单元形成的阵列，每个单元包括煅烧材料的存储元件和与存储元件串联连接的选择元件; 连接到所述单元的多个地址线; 连接到阵列的写阶段和阅读阶段。 写入级由电流发生器形成，电流发生器向所选择的单元提供预设电流，以便改变存储元件的电阻。 读取通过适当地偏置所选择的单元并将其中流动的电流与参考值进行比较来进行电压。

公开(公告)号：US20030223285A1

公开(公告)日：2003-12-04

申请号：US10331185

申请日：2002-12-27

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Osama Khouri ,  Ferdinando Bedeschi

IPC: G11C029/00

CPC classification number: G11C13/0026 ,  G11C7/22 ,  G11C13/0038 ,  G11C16/24 ,  G11C2216/22

Abstract: A nonvolatile memory device is described comprising a memory array, a row decoder and a column selector for addressing the memory cells of the memory array, and a biasing stage for biasing the array access device terminal of the addressed memory cell. The biasing stage is arranged between the column selector and the memory array and comprises a biasing transistor having a drain terminal connected to the column selector, a source terminal connected to the array access device terminal of the addressed memory cell, and a gate terminal receiving a logic driving signal, the logic levels of which are defined by precise and stable voltages and are generated by a logic block and an output buffer cascaded together. The output buffer may be supplied with either a read voltage or a program voltage supplied by a multiplexer. The biasing transistor may be either included as part of the column selector and formed by the selection transistor which is closest to the addressed memory cell or distinct from the selection transistors of the column selector.

Abstract translation: 描述了一种非易失性存储器件，其包括用于寻址存储器阵列的存储单元的存储器阵列，行解码器和列选择器，以及用于偏置寻址的存储器单元的阵列存取器件端子的偏置级。 偏置级布置在列选择器和存储器阵列之间，并且包括偏置晶体管，漏极端子连接到列选择器，源极端子连接到寻址存储单元的阵列存取器件端子，栅极端子接收 逻辑驱动信号，其逻辑电平由精确和稳定的电压定义，并由逻辑块和输出缓冲器一起级联产生。 可以向输出缓冲器提供由多路复用器提供的读取电压或编程电压。 偏置晶体管可以被包括为列选择器的一部分，并且由选择晶体管形成，该选择晶体管最靠近寻址的存储单元或与列选择器的选择晶体管不同。

公开(公告)号：US20040211953A1

公开(公告)日：2004-10-28

申请号：US10756195

申请日：2004-01-13

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Osama Khouri ,  Giorgio Pollaccia ,  Fabio Pellizzer

IPC: H01L047/00 ,  H01L021/336 ,  H01L021/4763

CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L45/122 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/16

Abstract: A contact structure for a PCM device is formed by an elongated formation having a longitudinal extension parallel to the upper surface of the body and an end face extending in a vertical plane. The end face is in contact with a bottom portion of an active region of chalcogenic material so that the dimensions of the contact area defined by the end face are determined by the thickness of the elongated formation and by the width thereof.

Abstract translation: 用于PCM装置的接触结构通过具有平行于主体的上表面的纵向延伸的细长结构和在垂直平面中延伸的端面形成。 端面与​​硫属活性材料的活性区域的底部接触，使得由端面限定的接触面积的尺寸由细长结构体的厚度及其宽度确定。

公开(公告)号：US20030185047A1

公开(公告)日：2003-10-02

申请号：US10319439

申请日：2002-12-12

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Osama Khouri ,  Ferdinando Bedeschi ,  Giorgio Bosisio ,  Fabio Pellizzer

IPC: G11C011/00

CPC classification number: G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

Abstract: The phase-change nonvolatile memory array is formed by a plurality of memory cells extending in a first and in a second direction orthogonal to each other. A plurality of column-selection lines extend parallel to the first direction. A plurality of word-selection lines extend parallel to the second direction. Each memory cell includes a PCM storage element and a selection transistor. A first terminal of the selection transistor is connected to a first terminal of the PCM storage element, and the control terminal of the selection transistor is connected to a respective word-selection line. A second terminal of the PCM storage element is connected to a respective column-selection line, and a second terminal of the selection transistor is connected to a reference-potential region while reading and programming the memory cells.

Abstract translation: 相变非易失性存储器阵列由在彼此正交的第一和第二方向上延伸的多个存储单元形成。 多个列选择线平行于第一方向延伸。 多个字选择线平行于第二方向延伸。 每个存储单元包括PCM存储元件和选择晶体管。 选择晶体管的第一端子连接到PCM存储元件的第一端子，并且选择晶体管的控制端子连接到相应的字选择线。 PCM存储元件的第二端子连接到相应的列选择线，并且在读取和编程存储器单元的同时，选择晶体管的第二端子连接到参考电位区域。