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1.发明申请公开(公告)号：US20200259474A1
公开(公告)日：2020-08-13
申请号：US16781493
申请日：2020-02-04
Applicant: STMicroelectronics S.r.l.
Inventor： Calogero Marco IPPOLITO , Michele VAIANA , Angelo RECCHIA
Abstract: An amplification interface includes a drain of a first FET connected to a first node, a drain of a second FET connected to a second node, and sources of the first and second FETs connected to a third node. First and second bias-current generators are connected to the first and second nodes. A third FET is connected between the third node and a reference voltage. A regulation circuit drives the gate of the third FET to regulate the common mode of the voltage at the first node and the voltage at the second node to a desired value. A current generator applies a correction current to the first and/or second node. A differential current integrator has a first and second inputs connected to the second and first nodes. The integrator supplies a voltage representing the integral of the difference between the currents received at the second and first inputs.
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2.发明申请公开(公告)号：US20200256898A1
公开(公告)日：2020-08-13
申请号：US16781598
申请日：2020-02-04
Applicant: STMicroelectronics S.r.l.
Inventor： Michele VAIANA , Calogero Marco IPPOLITO , Angelo RECCHIA , Antonio CICERO , Pierpaolo LOMBARDO
Abstract: An amplification interface includes an input terminal receiving a sensor current and an output terminal supplying an output voltage. An analog integrator is connected to the input terminal and supplies the output voltage. A current generator is connected to the input of the analog integrator and generates a compensation current based on a drive signal. A control circuit generates the drive signal for the current generator based on a control signal representing an offset in the sensor current supplied by the sensor. The current generator generates, based on the driving signal, a positive or negative current. The control circuit determines a first duration and a second duration as a function of the control signal representing the offset in the sensor current, during the measurement interval, and sets the driving signal to a first logic value for the first duration and to a second logic value for the second duration.
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公开(公告)号：US20240106401A1
公开(公告)日：2024-03-28
申请号：US18369583
申请日：2023-09-18
Applicant: STMicroelectronics S.r.l.
Inventor： Germano NICOLLINI , Michele VAIANA
CPC classification number: H03F3/45475 , H03F1/26 , H03F3/45273 , H03F2200/261
Abstract: A measurement system, featuring first and second capacitances, and switching, control, and measurement circuits, charges/discharges the capacitances during normal operation. The switching and control circuits periodically connect a first terminal of the first capacitance to a first voltage and a reference voltage, and a first terminal of the second capacitance to a second voltage and the reference voltage. The second terminal of the first capacitance and the second terminal of the second capacitance are connected to the input terminals of the differential integrator, the charge difference between the capacitances being transferred to the differential integrator. A comparator triggers when the output signal of the differential integrator exceeds the hysteresis threshold of the comparator. Two decoupling capacitances are connected between the input of the comparator and the output of the differential integrator, and two reset phases are used to store various disturbances to these decoupling capacitances, improving precision.
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公开(公告)号：US20160347606A1
公开(公告)日：2016-12-01
申请号：US14962945
申请日：2015-12-08
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Giuseppe BRUNO , Sebastiano CONTI , Mario CHIRICOSTA , Michele VAIANA , Calogero Marco IPPOLITO , Mario MAIORE , Daniele CASELLA
IPC: B81B7/00
CPC classification number: B81B7/007 , B81B7/02 , B81B2201/0264 , B81B2201/0292 , B81B2207/094 , G01L19/0092 , G01N27/223 , H01L23/3121 , H01L2224/32145 , H01L2224/48091 , H01L2224/73265 , H01L2924/181 , H01L2924/00012 , H01L2924/00014
Abstract: A packaged sensor assembly includes: a packaging structure, having at least one opening; a humidity sensor and a pressure sensor, which are housed inside the packaging structure and communicate fluidically with the outside through the opening, and a control circuit, operatively coupled to the humidity sensor and to the pressure sensor; wherein the humidity sensor and the control circuit are integrated in a first chip, and the pressure sensor is integrated in a second chip distinct from the first chip and bonded to the first chip.
Abstract translation: 包装传感器组件包括：具有至少一个开口的包装结构; 湿度传感器和压力传感器，其容纳在包装结构内并通过开口与外部流体连通;以及控制电路，可操作地耦合到湿度传感器和压力传感器; 其中所述湿度传感器和所述控制电路集成在第一芯片中，并且所述压力传感器集成在与所述第一芯片不同的第二芯片中并且被结合到所述第一芯片。
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公开(公告)号：US20240036595A1
公开(公告)日：2024-02-01
申请号：US18224897
申请日：2023-07-21
Applicant: STMicroelectronics S.r.l.
Inventor： Umberto FERLITO , Michele VAIANA , Giuseppe BRUNO , Alfio Dario GRASSO
Abstract: A low-drop out voltage regulator includes a pass element arranged between an input terminal and an output terminal, a feedback network configured to produce a feedback voltage derived from an output voltage, and an error amplifier configured to drive the pass element as a function of a difference between the feedback voltage and a reference voltage. An output transistor coupled in series with the pass element is controlled by a mode selection circuit. In response to assertion of a mode selection signal, the mode selection circuit turns on the output transistor to sink a current with a controlled magnitude from the output node. In response to de-assertion of the mode selection signal, the mode selection circuit sinks a current with a controlled magnitude from a control terminal of the output transistor to turn off the output transistor at a controlled rate.
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Patent Agency Ranking
公开(公告)号：US20220170795A1
公开(公告)日：2022-06-02
申请号：US17537074
申请日：2021-11-29
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Giuseppe BRUNO , Michele VAIANA , Maria Eloisa CASTAGNA , Angelo RECCHIA
Abstract: A thermographic sensor is proposed. The thermographic sensor includes one or more thermo-couples, each for providing a sensing voltage depending on a difference between a temperature of a hot joint and a temperature of a cold joint of the thermo-couple; the thermographic sensor further comprises one or more sensing transistors, each driven according to the sensing voltages of one or more corresponding thermo-couples for providing a sensing electrical signal depending on its temperature and on the corresponding sensing voltages. A thermographic device including the thermographic sensor and a corresponding signal processing circuit, and a system including one or more thermographic devices are also proposed.
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7.发明申请公开(公告)号：US20220163383A1
公开(公告)日：2022-05-26
申请号：US17530785
申请日：2021-11-19
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Michele VAIANA , Enri DUQI , Maria Eloisa CASTAGNA
Abstract: Radiation sensor including a detection assembly and a chopper assembly, which are mechanically coupled to delimit a main cavity; and wherein the chopper assembly includes: a suspended movable structure, which extends in the main cavity; and an actuation structure, which is electrically controllable to cause a change of position of the suspended movable structure. The detection unit includes a detection structure, which faces the main cavity and includes a number of detection devices. The suspended movable structure includes a first shield of conductive material, which shields the detection devices from the radiation, the shielding of the detection devices being a function of the position of the suspended movable structure.
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公开(公告)号：US20180313699A1
公开(公告)日：2018-11-01
申请号：US15957999
申请日：2018-04-20
Applicant: STMicroelectronics S.r.l.
Inventor： Michele VAIANA , Paolo PESENTI , Mario CHIRICOSTA , Calogero Marco IPPOLITO , Mario MAIORE
CPC classification number: G01K3/14 , G01K7/02 , G01K7/021 , H03H17/02 , H03M3/43 , H03M3/456 , H03M3/458
Abstract: A circuit includes a first input terminal, a second input terminal, a third input terminal and an output terminal. A first summation node adds signals at the first and third input terminals. A second summation node subtracts signals at the second and third input terminals. A selector selects between the added signals and subtracted signals in response to a selection signal. The output of the selector is integrated to generate an integrated signal. The integrated signal is compared by a comparator to a threshold, the comparator generating an output signal at the output terminal having a first level and a second level. Feedback of the output signal produces the selection signal causing the selector to select the added signals in response to the first level of the output signal and causing the selector to select the subtracted signals in response to the second level of the output signal.
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公开(公告)号：US20240106451A1
公开(公告)日：2024-03-28
申请号：US18370052
申请日：2023-09-19
Applicant: STMicroelectronics S.r.l.
Inventor： Calogero Marco IPPOLITO , Michele VAIANA
CPC classification number: H03M1/1255 , H03M1/1215 , H03M3/454 , H03M3/462
Abstract: A differential pair of FETs forms a sensor circuit coupled to a differential current reading circuit that includes a current to voltage converter and an analog to digital converter. An ESD protection circuit interposed between the sensor circuit and the differential current reading circuit adds spurious currents to a differential sensor current output by the sensor circuit. A circuit before the ESD protection circuit switches the sign of the differential sensor current according to a period of complementary phase clock signals which correspond to a sampling interval of the analog to digital converter. A circuit selects signals depending on the value of the period of the phase clock signals to eliminate the spurious currents.
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10.发明申请公开(公告)号：US20220377260A1
公开(公告)日：2022-11-24
申请号：US17745465
申请日：2022-05-16
Applicant: STMicroelectronics S.r.l.
Inventor： Pierpaolo LOMBARDO , Michele VAIANA
Abstract: Current signals indicative of sensed physical quantities are collected from sensing transistors in an array of sensing transistors. The sensing transistors have respective control nodes and current channel paths therethrough between respective first nodes and a second node common to the sensing transistors. A bias voltage level is applied to the respective first nodes of the sensing transistors in the array and one sensing transistor in the array of sensing transistors is selected. The selected sensing transistor is decoupled from the bias voltage level, while the remaining sensing transistors in the array of sensing transistors maintain coupling to the bias voltage level. The respective first node of the selected sensing transistor in the array of sensing transistors is coupled to an output node, and an output current signal is collected from the output node.
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