公开(公告)号：US11621051B2

公开(公告)日：2023-04-04

申请号：US17647793

申请日：2022-01-12

Applicant: STMicroelectronics (Rousset) SAS ,  STMICROELECTRONICS SA

Inventor： Stephane Denorme ,  Philippe Candelier ,  Joel Damiens ,  Fabrice Marinet

IPC: G11C11/34 ,  G11C29/52 ,  G11C17/12

Abstract: A device includes a first switch, a first irreversibly programmable memory point, and a second irreversibly programmable memory point coupled in parallel with the first irreversibly programmable memory point. The first switch and the parallel combination of the first and second irreversibly programmable memory points are coupled in series between a first node and a second node.

公开(公告)号：US11250930B2

公开(公告)日：2022-02-15

申请号：US16709019

申请日：2019-12-10

Applicant: STMicroelectronics SA ,  STMicroelectronics (Rousset) SAS

Inventor： Stephane Denorme ,  Philippe Candelier ,  Joel Damiens ,  Fabrice Marinet

IPC: G11C17/00 ,  G11C29/52 ,  G11C17/12

Abstract: A device includes a first switch, a first irreversibly programmable memory point, and a second irreversibly programmable memory point coupled in parallel with the first irreversibly programmable memory point. The first switch and the parallel combination of the first and second irreversibly programmable memory points are coupled in series between a first node and a second node.

公开(公告)号：US20220139491A1

公开(公告)日：2022-05-05

申请号：US17647793

申请日：2022-01-12

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics SA

Inventor： Stephane Denorme ,  Philippe Candelier ,  Joel Damiens ,  Fabrice Marinet

IPC: G11C29/52 ,  G11C17/12

Abstract: A device includes a first switch, a first irreversibly programmable memory point, and a second irreversibly programmable memory point coupled in parallel with the first irreversibly programmable memory point. The first switch and the parallel combination of the first and second irreversibly programmable memory points are coupled in series between a first node and a second node.

公开(公告)号：US09589968B2

公开(公告)日：2017-03-07

申请号：US14952662

申请日：2015-11-25

Applicant: STMicroelectronics SA

Inventor： Stéphane Denorme ,  Philippe Candelier

IPC: H01L27/112 ,  H01L29/66 ,  H01L21/28 ,  H01L29/40 ,  H01L29/49

CPC classification number: H01L27/11206 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/7624 ,  H01L21/823418 ,  H01L21/84 ,  H01L23/5252 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/4933 ,  H01L29/4975 ,  H01L29/66181 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a silicon on insulator substrate having a semiconductor film located above a buried insulating layer. At least one memory cell of the one-time-programmable type includes an MOS capacitor having a first electrode region including a gate region at least partially silicided and flanked by an insulating lateral region, a dielectric layer located between the gate region and the semiconductor film, and a second electrode region including a silicided zone of the semiconductor film, located alongside the insulating lateral region and extending at least partially under the dielectric layer.

Abstract translation: 集成电路包括具有位于掩埋绝缘层上方的半导体膜的绝缘体上硅衬底。 一次可编程类型的至少一个存储单元包括具有第一电极区域的MOS电容器，该第一电极区域包括至少部分硅化并且侧壁为绝缘横向区域的栅极区域，位于栅极区域和半导体膜之间的电介质层 以及包括半导体膜的硅化物区域的第二电极区域，位于绝缘横向区域旁边并且至少部分地延伸到介电层下方。

公开(公告)号：US20150364209A1

公开(公告)日：2015-12-17

申请号：US14832802

申请日：2015-08-21

Applicant: STMicroelectronics SA

Inventor： Philippe Candelier ,  Joel Damiens ,  Elise Le Roux

IPC: G11C17/16 ,  H01L27/112 ,  G11C17/18

CPC classification number: G11C17/165 ,  G11C17/18 ,  H01L27/101 ,  H01L27/11206

Abstract: A method for controlling the breakdown of an antifuse memory cell formed on a semiconductor substrate, including the steps of: applying a programming voltage; detecting a breakdown time; and interrupting the application of the programming voltage at a time following the breakdown time by a post-breakdown time.

Abstract translation: 一种用于控制形成在半导体衬底上的反熔层存储单元击穿的方法，包括以下步骤：施加编程电压; 检测故障时间; 并且在故障时间之后的故障时间之后中断施加编程电压。

公开(公告)号：US11164647B2

公开(公告)日：2021-11-02

申请号：US16713947

申请日：2019-12-13

Applicant: STMicroelectronics SA

Inventor： Stephane Denorme ,  Philippe Candelier

IPC: G11C5/06 ,  G11C17/12 ,  H01L27/112 ,  G11C5/02

Abstract: A device includes a number of irreversibly programmable memory points. Each irreversibly programmable memory point includes a first semiconductor zone and a gate located on the first zone. A conductive area defines the gates of the memory points. First and second semiconductor areas are respectively located on either side of a vertical alignment with the conductive area. The first zones are alternately in contact with the first and second areas.

公开(公告)号：US09142318B2

公开(公告)日：2015-09-22

申请号：US13887167

申请日：2013-05-03

Applicant: STMicroelectronics SA

Inventor： Philippe Candelier ,  Joel Damiens ,  Elise Leroux

IPC: G11C17/16 ,  G11C17/18 ,  H01L27/112 ,  H01L27/10

CPC classification number: G11C17/165 ,  G11C17/18 ,  H01L27/101 ,  H01L27/11206

Abstract: A method for controlling the breakdown of an antifuse memory cell formed on a semiconductor substrate, including the steps of: applying a programming voltage; detecting a breakdown time; and interrupting the application of the programming voltage at a time following the breakdown time by a post-breakdown time.

Abstract translation: 一种用于控制形成在半导体衬底上的反熔层存储单元击穿的方法，包括以下步骤：施加编程电压; 检测故障时间; 并且在故障时间之后的故障时间之后中断施加编程电压。

公开(公告)号：US20150085560A1

公开(公告)日：2015-03-26

申请号：US14494383

申请日：2014-09-23

Applicant: STMicroelectronics SA

Inventor： Philippe Candelier ,  Thérèse Andrée Diokh ,  Joel Damiens ,  Elise Le Roux

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C13/0033 ,  G11C13/004 ,  G11C14/009 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2013/009 ,  G11C2213/79

Abstract: A method of controlling an array of ReRAM cells including programmable-resistance storage elements, including: during a standby period, applying a non-zero standby voltage between electrodes of the storage elements of each cell of the array.

Abstract translation: 一种控制包括可编程电阻存储元件的ReRAM单元阵列的方法，包括：在待机期间，在阵列的每个单元的存储元件的电极之间施加非零备用电压。

公开(公告)号：US20170133390A1

公开(公告)日：2017-05-11

申请号：US15413497

申请日：2017-01-24

Applicant: STMicroelectronics SA

Inventor： Stéphane Denorme ,  Philippe Candelier

IPC: H01L27/112 ,  H01L29/40 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L29/49 ,  H01L21/28

CPC classification number: H01L27/11206 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/7624 ,  H01L21/823418 ,  H01L21/84 ,  H01L23/5252 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/4933 ,  H01L29/4975 ,  H01L29/66181 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a silicon-on-insulator substrate that includes a semiconductor film located above a buried insulating layer. A first electrode of a silicide material overlies the semiconductor film. A sidewall insulating material is disposed along sidewalls of the first electrode. A dielectric layer is located between the first electrode and the semiconductor film. A second electrode includes a silicided zone of the semiconductor film, which is located alongside the sidewall insulating material and extends at least partially under the dielectric layer and the first electrode. The first electrode, the dielectric layer and the second electrode form a capacitor that is part of a circuit of the integrated circuit.

公开(公告)号：US09564242B2

公开(公告)日：2017-02-07

申请号：US14832802

申请日：2015-08-21

Applicant: STMicroelectronics SA

Inventor： Philippe Candelier ,  Joel Damiens ,  Elise Le Roux

IPC: G11C17/16 ,  G11C17/18 ,  H01L27/12 ,  H01L27/112 ,  H01L27/10

CPC classification number: G11C17/165 ,  G11C17/18 ,  H01L27/101 ,  H01L27/11206

Abstract: A method for controlling the breakdown of an antifuse memory cell formed on a semiconductor substrate, including the steps of: applying a programming voltage; detecting a breakdown time; and interrupting the application of the programming voltage at a time following the breakdown time by a post-breakdown time.

Abstract translation: 一种用于控制形成在半导体衬底上的反熔层存储单元击穿的方法，包括以下步骤：施加编程电压; 检测故障时间; 并且在故障时间之后的故障时间之后中断施加编程电压。