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公开(公告)号：US20170347464A1
公开(公告)日：2017-11-30
申请号：US15536809
申请日：2015-12-21
Inventor： Kayo HASHIZUME , Yoshio OKA , Takashi KASUGA , Jinjoo PARK , Kousuke MIURA , Hiroshi UEDA
CPC classification number: H05K1/092 , B32B15/08 , B32B15/088 , H05K1/0298 , H05K1/03 , H05K1/05 , H05K1/09 , H05K3/1283 , H05K3/182 , H05K3/24 , H05K3/38 , H05K3/381 , H05K2201/0154 , H05K2203/025 , H05K2203/095
Abstract: An object is to provide a substrate for a printed wiring board that has good circuit formability while maintaining adhesion strength between a conductive layer (2) and a base film (1). The substrate includes a base film having an insulating property (1) and a conductive layer (2) formed on at least one surface of the base film (1). The maximum height Sz, which is defined in ISO25178, of the surface of the base film (1) is 0.05 μm or more and less than 0.9 μm.
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2.发明申请公开(公告)号：US20170347449A1
公开(公告)日：2017-11-30
申请号：US15536954
申请日：2015-12-18
Inventor： Motohiko SUGIURA , Takashi KASUGA , Yoshio OKA , Shigeaki UEMURA , Jinjoo PARK , Hiroshi UEDA , Kousuke MIURA
CPC classification number: H05K1/097 , B82Y30/00 , B82Y40/00 , H05K1/0298 , H05K1/03 , H05K1/05 , H05K1/09 , H05K3/24 , H05K3/38 , H05K3/388 , H05K2201/0209 , H05K2201/0257 , H05K2201/0266 , H05K2201/0269
Abstract: A substrate for a printed circuit board according to an embodiment of the present invention includes a base film having an insulating property, and a metal layer formed on at least one surface side of the base film. In the substrate for a printed circuit board, a plurality of fine particles are disposed between the base film and the metal layer, and the fine particles are formed of a metal the same as a main metal of the metal layer or formed of a metal compound of the main metal. The fine particles preferably have an average particle size of 0.1 nm or more and 20 nm or less. The fine particles are preferably formed of a metal oxide or a metal hydroxide. The fine particles are preferably present between the base film and the metal layer so as to form a layer. The metal layer preferably includes a metal grain layer formed by firing metal nanoparticles.
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3.发明申请公开(公告)号：US20170127516A1
公开(公告)日：2017-05-04
申请号：US15127165
申请日：2015-03-19
Inventor： Takashi KASUGA , Yoshio OKA , Shigeyoshi NAKAYAMA , Jinjoo PARK , Sumito UEHARA , Kousuke MIURA , Hiroshi UEDA
CPC classification number: H05K1/092 , H05K1/05 , H05K3/022 , H05K3/108 , H05K3/38 , H05K3/384 , H05K2201/0154 , H05K2201/0257 , H05K2203/0709 , H05K2203/072
Abstract: A substrate for a printed circuit board includes a base film having an insulating property; a first conductive layer formed on at least one of surfaces of the base film by application of a conductive ink containing metal particles; and a second conductive layer formed, by plating, on a surface of the first conductive layer, the surface being on a side opposite to the base film, wherein a region near an interface between the base film and the first conductive layer contains a metal oxide species based on a metal of the metal particles and a metal hydroxide species based on the metal of the metal particles, the metal oxide species in the region near the interface between the base film and the first conductive layer has a mass per unit area of 0.1 μg/cm2 or more and 10 μg/cm2 or less, and a mass ratio of the metal oxide species to the metal hydroxide species is 0.1 or more.
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公开(公告)号：US20210392754A1
公开(公告)日：2021-12-16
申请号：US17446333
申请日：2021-08-30
Inventor： Kohei OKAMOTO , Kousuke MIURA , Hiroshi UEDA , Shoichiro SAKAI , Maki IKEBE
Abstract: A printed wiring board according to as aspect of the present invention includes a base film having insulation properties and a conductive pattern including multiple wiring portions laminated, the conductive pattern running on at least one surface of the base film, wherein each wiring portion includes a first conductive portion and a second conductive portion coating an outer surface of the first conductive portion, wherein an average width of each wiring portion is 10 μm or greater to 50 μm or smaller, and an average thickness of the second conductive portion is 1 μm or greater to smaller than 8.5 μm.
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5.发明申请公开(公告)号：US20200015353A1
公开(公告)日：2020-01-09
申请号：US16495234
申请日：2018-02-07
Inventor： Kenji TAKAHASHI , Kouji NITTA , Shoichiro SAKAI , Junichi MOTOMURA , Maki IKEBE , Kousuke MIURA , Masahiro ITOU
Abstract: A base material for printed interconnect boards according to one aspect of the present invention includes a base film; and at least one conductive layer that is layered on the base film. The base material for printed interconnect boards includes a product in which a plurality of interconnect board pieces are regularly arrayed in plan view and includes an outer frame region surrounding the product. The outer frame region includes a proximity region within 5 mm from an outer edge of the product and includes an outside region other than the proximity region. A layered conductive layer area rate of the proximity region is smaller than a layered conductive layer area rate of the product.
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Patent Agency Ranking
公开(公告)号：US20190008037A1
公开(公告)日：2019-01-03
申请号：US15752359
申请日：2016-08-01
Inventor： Kohei OKAMOTO , Kousuke MIURA , Hiroshi UEDA , Takashi KASUGA , Kazuhiro MIYATA
Abstract: A printed circuit board according to an embodiment of the present invention includes a base film having an insulating property and a conductive pattern disposed on at least one surface of the base film. The conductive pattern includes a copper particle bond layer which is fixed to the base film, and a lightness L* of a conductive pattern non-formed region of the base film is 60 or less. The base film may include a modified layer on one surface side thereof.
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7.发明申请公开(公告)号：US20180014403A1
公开(公告)日：2018-01-11
申请号：US15544961
申请日：2016-01-19
Inventor： Takashi KASUGA , Yoshio OKA , Shigeaki UEMURA , Jinjoo PARK , Hiroshi UEDA , Kousuke MIURA
IPC: H05K1/02 , H05K3/40 , H05K3/18 , H05K3/10 , C23C28/02 , H05K3/06 , H05K3/02 , H05K1/09 , H05K3/42 , H05K3/12
CPC classification number: H05K1/0298 , C23C28/023 , H05K1/09 , H05K1/097 , H05K3/025 , H05K3/064 , H05K3/108 , H05K3/1283 , H05K3/188 , H05K3/245 , H05K3/381 , H05K3/4038 , H05K3/424 , H05K2201/0116 , H05K2201/0141 , H05K2201/0145 , H05K2201/0154 , H05K2203/072 , H05K2203/095 , H05K2203/1131
Abstract: A substrate for a printed circuit board according to an embodiment of the present invention includes a base film having insulating properties and a sintered layer formed of a plurality of metal particles, the sintered layer being stacked on at least one surface of the base film, in which a region of the sintered layer extending from an interface between the sintered layer and the base film to a position 500 nm or less from the interface has a porosity of 1% or more and 50% or less.
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公开(公告)号：US20240200220A1
公开(公告)日：2024-06-20
申请号：US18286999
申请日：2022-04-13
Inventor： Kousuke MIURA , Koji NITTA , Shoichiro SAKAI
CPC classification number: C25D7/06 , H05K3/18 , H05K2203/0723 , H05K2203/1545
Abstract: A wet treatment apparatus is configured to treat a continuously moving sheet-shaped workpiece and includes a wet treatment tank including a side surface portion having a first slit, a pair of rolls located outside the wet treatment tank, the pair of rolls being spaced apart from the first slit and being arranged in such a manner as to nip the workpiece in a transverse direction, and a pair of treatment-liquid shield members disposed on a side opposite to a side on which the wet treatment tank is disposed with the pair of rolls interposed between the pair of treatment-liquid shield members and the wet treatment tank in a movement direction of the workpiece. In a direction parallel to a width of the first slit, a width of the shield member is larger than a width of the roll.
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公开(公告)号：US20200236791A1
公开(公告)日：2020-07-23
申请号：US16621447
申请日：2018-05-21
Inventor： Junichi MOTOMURA , Koji NITTA , Shoichiro SAKAI , Kenji TAKAHASHI , Maki IKEBE , Kousuke MIURA , Masahiro ITOH
Abstract: A printed wiring board production method that forms a base film and a conductive pattern on the base film by an additive method or a subtractive method, includes a plating process that electroplates the conductive pattern on a surface of the base film, wherein the plating process includes a shield plate arranging process that arranges a shield plate between an anode and a printed wiring board substrate that forms a cathode, and a substrate arranging process that arranges the printed wiring board substrate in a plating tank, and wherein a distance between the shield plate and the printed wiring board substrate is 50 mm or greater and 150 mm or less.
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公开(公告)号：US20180054900A1
公开(公告)日：2018-02-22
申请号：US15557255
申请日：2016-03-10
Applicant: SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
Inventor： Hiroshi UEDA , Kousuke MIURA , Yoshihito YAMAGUCHI , Yuka URABE
CPC classification number: H05K3/4673 , H01F17/0013 , H01F27/327 , H01F41/041 , H01F41/043 , H01F41/127 , H01F2017/0073 , H05K1/165 , H05K3/241 , H05K3/4626 , H05K3/4644 , H05K2203/1476 , H05K2203/1572
Abstract: A planar coil element of the present invention includes an insulating base film having a first surface and a second surface opposite to the first surface, a first conductive pattern deposited on the first surface side of the insulating base film, and a first insulating layer covering the first conductive pattern on the first surface side, in which the first conductive pattern includes a core body and a widening layer deposited by plating on the outer surface of the core body, and the ratio of the average thickness of the first conductive pattern to the average circuit pitch of the first conductive pattern is ½ or more and 5 or less.
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