公开(公告)号：US20230005842A1

公开(公告)日：2023-01-05

申请号：US17828799

申请日：2022-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MINJUNG KIM ,  DONGKYU KIM ,  JONGYOUN KIM ,  SEOKHYUN LEE ,  JAEGWON JANG

IPC: H01L23/538 ,  H01L25/18

Abstract: A semiconductor package includes a substrate; and a first semiconductor device and a second semiconductor device that are provided on the substrate. The substrate includes a first dielectric layer and a second dielectric layer provided on the first dielectric layer, a plurality of signal lines provided between the first dielectric layer and the second dielectric layer and connecting the first semiconductor device to the second semiconductor device, and a conductive pad and a conductive plate provided on the second dielectric layer. The conductive pad overlaps the first semiconductor device or the second semiconductor device. The conductive plate overlaps the signal lines.

公开(公告)号：US20210028137A1

公开(公告)日：2021-01-28

申请号：US16795733

申请日：2020-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： GWANGJAE JEON ,  DONGKYU KIM ,  JUNG-HO PARK ,  YEONHO JANG

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/498 ,  H01L23/31

Abstract: Disclosed is a semiconductor package comprising a redistribution substrate, and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern, a lower dielectric layer that covers a sidewall of the under-bump pattern, and a first redistribution pattern on the lower dielectric layer. The first redistribution pattern includes a first line part. A width at a top surface of the under-bump pattern is greater than a width at a bottom surface of the under-bump pattern. A thickness of the under-bump pattern is greater than a thickness of the first line part.

公开(公告)号：US20240178185A1

公开(公告)日：2024-05-30

申请号：US18357484

申请日：2023-07-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGKYU KIM ,  KYUNG DON MUN ,  KYOUNG LIM SUK ,  HYEONJEONG HWANG

IPC: H01L25/065 ,  H01L23/373 ,  H01L23/538 ,  H10B80/00

CPC classification number: H01L25/0652 ,  H01L23/3736 ,  H01L23/5383 ,  H01L23/5384 ,  H10B80/00

Abstract: Disclosed is a semiconductor package comprising a lower circuit part having a first region and a second region horizontally offset from each other and including a connection structure within the first region and a logic chip within the second region, a memory structure that overlaps the connection structure in a vertical direction, and a thermal radiation structure that overlaps the logic chip in the vertical direction. The logic chip and the memory structure are spaced apart in a horizontal direction parallel to a top surface of the logic chip.

公开(公告)号：US20230141318A1

公开(公告)日：2023-05-11

申请号：US17879106

申请日：2022-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYEONJEONG HWANG ,  DONGKYU KIM ,  KYOUNG LIM SUK ,  WONJAE LEE

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L23/5386 ,  H01L25/0652 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16

Abstract: A redistribution substrate may include a first interconnection layer having a first insulating pattern, a first dummy pattern and a second dummy pattern, the first and second dummy patterns being in the first insulating pattern, and a second interconnection layer stacked on the first interconnection layer, the second interconnection layer having a second insulating pattern, a signal pattern and a power/ground pattern, the signal and power/ground patterns being in the second insulating pattern. The first dummy pattern may be located below the signal pattern, and the second dummy pattern may be located below the power/ground pattern. The first dummy pattern may include dot patterns, and the second dummy pattern may include a plate pattern.

公开(公告)号：US20220285328A1

公开(公告)日：2022-09-08

申请号：US17648424

申请日：2022-01-20

Applicant: Samsung Electronics Co., LTD

Inventor： DONGKYU KIM ,  Daeho Lee ,  Seokhyun Lee ,  Minjung Kim ,  Taewon Yoo

IPC: H01L25/10 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor package includes a lower semiconductor chip disposed on a lower redistribution substrate, lower solder patterns disposed between the lower redistribution substrate and the lower semiconductor chip, conductive structures disposed on the lower redistribution substrate, a lower molding layer disposed on the lower redistribution substrate and covering a top surface of the lower semiconductor chip, an upper redistribution substrate disposed on the lower molding layer and electrically connected to the conductive structures, an upper semiconductor chip disposed on the upper redistribution substrate, upper solder patterns disposed between the upper redistribution substrate and the upper semiconductor chip, and an upper molding layer disposed on the upper redistribution substrate and covering a sidewall of the upper semiconductor chip. The number of the conductive structures is greater than that of chip pads of the upper semiconductor chip.

公开(公告)号：US20240128145A1

公开(公告)日：2024-04-18

申请号：US18469111

申请日：2023-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYEONSEOK LEE ,  DONGKYU KIM ,  HYEONJEONG HWANG

IPC: H01L23/367 ,  H01L21/306 ,  H01L21/308 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H10B80/00

CPC classification number: H01L23/367 ,  H01L21/30608 ,  H01L21/3086 ,  H01L21/4878 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3738 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/95 ,  H01L25/0655 ,  H01L25/105 ,  H10B80/00 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/95 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15174 ,  H01L2924/3511

Abstract: A semiconductor package includes a redistribution substrate, a sub-package disposed on the redistribution substrate, a semiconductor chip disposed on the redistribution substrate, a heat dissipation structure disposed on the redistribution substrate and surrounding the sub-package and the semiconductor chip, and an encapsulant. The redistribution substrate includes a redistribution structure. The semiconductor chip is positioned side-by-side with the sub-package. The encapsulant encapsulates the sub-package, the semiconductor chip, and the heat dissipation structure.

公开(公告)号：US20230215799A1

公开(公告)日：2023-07-06

申请号：US18183062

申请日：2023-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYOUNG LIM SUK ,  KEUNG BEUM KIM ,  DONGKYU KIM ,  MINJUNG KIM ,  SEOKHYUN LEE

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L25/105 ,  H01L23/5386 ,  H01L23/5383 ,  H01L23/49822 ,  H01L21/4857 ,  H01L2924/14361 ,  H01L24/16 ,  H01L24/73 ,  H01L24/17 ,  H01L2924/1431 ,  H01L2224/08225 ,  H01L2924/1433 ,  H01L24/08 ,  H01L2225/1035 ,  H01L2224/16227 ,  H01L25/0652 ,  H01L25/18 ,  H01L24/33 ,  H01L2224/17181 ,  H01L2224/73253 ,  H01L2225/1058 ,  H01L2224/33181 ,  H01L2224/73204

Abstract: A semiconductor package includes a redistribution substrate and a semiconductor chip thereon. The redistribution substrate includes a ground under-bump pattern, signal under-bump patterns laterally spaced apart from the ground under-bump pattern, first signal line patterns disposed on the signal under-bump patterns and coupled to corresponding signal under-bump patterns, and a first ground pattern coupled to the ground under-bump pattern and laterally spaced apart from the first signal line pattern. Each of the signal and ground under-bump patterns includes a first part and a second part formed on the first part and that is wider than the first part. The second part of the ground under-bump pattern is wider than the second part of the signal under-bump pattern. The ground under-bump pattern vertically overlaps the first signal line patterns. The first ground pattern does not vertically overlap the signal under-bump patterns.

公开(公告)号：US20230065378A1

公开(公告)日：2023-03-02

申请号：US17680857

申请日：2022-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MINJUNG KIM ,  DONGKYU KIM ,  JONGYOUN KIM ,  SEOKHYUN LEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498

Abstract: A semiconductor package includes a first redistribution substrate, a lower semiconductor chip on the first redistribution substrate and a through via therein, a first lower conductive structure and a second lower conductive structure that are on the first redistribution substrate and are laterally spaced apart from the lower semiconductor chip, an upper semiconductor chip on the lower semiconductor chip and the second lower conductive structure and coupled to the through via and the second lower conductive structure, and an upper conductive structure on the first lower conductive structure. A width of the second lower conductive structure is greater than a width of the through via.

公开(公告)号：US20250167098A1

公开(公告)日：2025-05-22

申请号：US19029539

申请日：2025-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYOUNG LIM SUK ,  KEUNG BEUM KIM ,  DONGKYU KIM ,  MINJUNG KIM ,  SEOKHYUN LEE

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

Abstract: A semiconductor package includes a redistribution substrate and a semiconductor chip thereon. The redistribution substrate includes a ground under-bump pattern, signal under-bump patterns laterally spaced apart from the ground under-bump pattern, first signal line patterns disposed on the signal under-bump patterns and coupled to corresponding signal under-bump patterns, and a first ground pattern coupled to the ground under-bump pattern and laterally spaced apart from the first signal line pattern. Each of the signal and ground under-bump patterns includes a first part and a second part formed on the first part and that is wider than the first part. The second part of the ground under-bump pattern is wider than the second part of the signal under-bump pattern. The ground under-bump pattern vertically overlaps the first signal line patterns. The first ground pattern does not vertically overlap the signal under-bump patterns.

公开(公告)号：US20230065366A1

公开(公告)日：2023-03-02

申请号：US17806907

申请日：2022-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGKYU KIM ,  MINJUNG KIM ,  KYOUNG LIM SUK ,  SEOKHYUN LEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package includes a first redistribution substrate, a passive device mounted on a bottom surface of the first redistribution substrate, a first semiconductor chip disposed on a top surface of the first redistribution substrate, the first semiconductor chip including a through via disposed therein, a second semiconductor chip disposed on the first semiconductor chip, and a conductive post disposed between the top surface of the first redistribution substrate and a bottom surface of the second semiconductor chip and spaced apart from the first semiconductor chip. The conductive post is connected to the first redistribution substrate and to the second semiconductor chip. The conductive post overlaps with at least a portion of the passive device in a vertical direction normal to the top surface of the first redistribution substrate.