公开(公告)号：US11581026B2

公开(公告)日：2023-02-14

申请号：US17495862

申请日：2021-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemin Choi ,  Daehyun Kwon ,  Buyeon Lee

IPC: G11C7/02 ,  G11C7/06 ,  G11C7/10 ,  G11C16/24 ,  G11C16/08 ,  G11C7/22

Abstract: A data receiving device of a memory device comprises a first pre-amplifier configured to receive previous data, a first reference voltage, and input data, and to output differential signals by comparing the input data with the first reference voltage in response to a clock, when the first pre-amplifier is selected in response to the previous data, a second pre-amplifier configured to receive inverted previous data, a second reference voltage, different from the first reference voltage, and the input data, and outputting a common signal in response to the clock, when the second pre-amplifier is unselected in response to the previous data; and an amplifier configured to receive the differential signals and the common signal, and to latch the input data by amplifying the differential signals.

公开(公告)号：US20210174844A1

公开(公告)日：2021-06-10

申请号：US16930561

申请日：2020-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemin Choi ,  Daehyun Kwon ,  Buyeon Lee

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  G11C16/08 ,  G11C16/24

Abstract: A data receiving device of a memory device comprises a first pre-amplifier configured to receive previous data, a first reference voltage, and input data, and to output differential signals by comparing the input data with the first reference voltage in response to a clock, when the first pre-amplifier is selected in response to the previous data, a second pre-amplifier configured to receive inverted previous data, a second reference voltage, different from the first reference voltage, and the input data, and outputting a common signal in response to the clock, when the second pre-amplifier is unselected in response to the previous data; and an amplifier configured to receive the differential signals and the common signal, and to latch the input data by amplifying the differential signals.

公开(公告)号：US12033717B2

公开(公告)日：2024-07-09

申请号：US17903578

申请日：2022-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyeok Baek ,  Daehyun Kwon ,  Hyejung Kwon ,  Donggun An ,  Daewoong Lee

IPC: G11C7/10

CPC classification number: G11C7/1048 ,  G11C2207/2254

Abstract: A calibration circuit includes a first, second and third pull-up units each connected to a first power supply node, and first and second pull-down units each connected to a second power supply node. A first code generator is configured to generate a first code by comparing a voltage of a pad at which the first pull-up unit is connected to an external resistor with a reference voltage, and a second code generator is configured to generate a second code by comparing a voltage of a first intermediate node with the reference voltage and output the second code to the first and second pull-down units. A third code generator is configured to generate a third code by comparing a voltage of a second intermediate node between the second pull-down unit and the third pull-up unit with the reference voltage.

公开(公告)号：US11797450B2

公开(公告)日：2023-10-24

申请号：US17232844

申请日：2021-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoungsul Kim ,  Youngsan Kang ,  Daehyun Kwon ,  Myong-Seob Song ,  Byung Yo Lee ,  Yejin Jo

IPC: G06F12/0815 ,  G06F12/0804

CPC classification number: G06F12/0815 ,  G06F12/0804 ,  G06F2212/1032

Abstract: An electronic device includes a cache memory including a memory space for storing a first cache set including a plurality of sector data and a plurality of dirty bits, each of the plurality of dirty bits representing whether corresponding sector data of the plurality of sector data are modified, a memory controller, connected to a plurality of data lines and a data mask line, for receiving the plurality of sector data and the plurality of dirty bits from the cache memory, setting a logic level of a data mask signal based on a logic level of each of the plurality of dirty bits, and outputting the plurality of sector data through the plurality of data lines and the data mask signal through the data mask line, and a memory device, connected to the plurality of data lines and the data mask line, for receiving the plurality of sector data through the plurality of data lines, and receiving the data mask signal through the data mask line.

公开(公告)号：US20220028434A1

公开(公告)日：2022-01-27

申请号：US17495862

申请日：2021-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemin Choi ,  Daehyun Kwon ,  Buyeon Lee

IPC: G11C7/06 ,  G11C7/10 ,  G11C16/24 ,  G11C16/08 ,  G11C7/22

Abstract: A data receiving device of a memory device comprises a first pre-amplifier configured to receive previous data, a first reference voltage, and input data, and to output differential signals by comparing the input data with the first reference voltage in response to a clock, when the first pre-amplifier is selected in response to the previous data, a second pre-amplifier configured to receive inverted previous data, a second reference voltage, different from the first reference voltage, and the input data, and outputting a common signal in response to the clock, when the second pre-amplifier is unselected in response to the previous data; and an amplifier configured to receive the differential signals and the common signal, and to latch the input data by amplifying the differential signals.

公开(公告)号：US11170825B2

公开(公告)日：2021-11-09

申请号：US16930561

申请日：2020-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemin Choi ,  Daehyun Kwon ,  Buyeon Lee

IPC: G11C7/02 ,  G11C7/06 ,  G11C7/10 ,  G11C16/24 ,  G11C16/08 ,  G11C7/22

Abstract: A data receiving device of a memory device comprises a first pre-amplifier configured to receive previous data, a first reference voltage, and input data, and to output differential signals by comparing the input data with the first reference voltage in response to a clock, when the first pre-amplifier is selected in response to the previous data, a second pre-amplifier configured to receive inverted previous data, a second reference voltage, different from the first reference voltage, and the input data, and outputting a common signal in response to the clock, when the second pre-amplifier is unselected in response to the previous data; and an amplifier configured to receive the differential signals and the common signal, and to latch the input data by amplifying the differential signals.

公开(公告)号：US20230368824A1

公开(公告)日：2023-11-16

申请号：US18052976

申请日：2022-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanguk Lee ,  Daehyun Kwon ,  Jang-Woo Ryu ,  Hangi Jung

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/225

Abstract: An integrated circuit memory device includes a serializer configured to convert a plurality of bits of parallel read data, which are synchronized with a corresponding plurality of clock signals that are out-of-phase relative to each other, into a serial stream of the read data. This conversion is performed using a Boolean logic circuit, which is configured to receive each of the plurality of bits of parallel read data and each of the plurality of out-of-phase clock signals at corresponding inputs thereof.

公开(公告)号：US11747393B2

公开(公告)日：2023-09-05

申请号：US17703535

申请日：2022-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daehyun Kwon ,  Donghee Kim ,  Sungoh Huh

IPC: G01R31/28 ,  H01L23/48 ,  H01L23/522 ,  H01L25/065

CPC classification number: G01R31/2884 ,  H01L23/481 ,  H01L23/5227 ,  H01L25/0655

Abstract: An integrated circuit device, a semiconductor substrate, and a test system including the integrated circuit device are disclosed. The integrated circuit device includes a power terminal configured to receive a source voltage, a power via connected to the power terminal and passing through at least one of a number of layers, a number of inductive vias arranged apart from the power via and passing through at least one of the number of layers, a number of wirings connected to ends of at least some of the number of inductive vias and configured to form a coil wound in toroidal form together with the number of inductive vias, around the power via, and a test terminal configured to output an induced voltage in the coil externally of the integrated circuit device, in response to the supply of the source voltage.

公开(公告)号：US12237049B2

公开(公告)日：2025-02-25

申请号：US18052976

申请日：2022-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanguk Lee ,  Daehyun Kwon ,  Jang-Woo Ryu ,  Hangi Jung

IPC: G11C7/22 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4093

Abstract: An integrated circuit memory device includes a serializer configured to convert a plurality of bits of parallel read data, which are synchronized with a corresponding plurality of clock signals that are out-of-phase relative to each other, into a serial stream of the read data. This conversion is performed using a Boolean logic circuit, which is configured to receive each of the plurality of bits of parallel read data and each of the plurality of out-of-phase clock signals at corresponding inputs thereof.

公开(公告)号：US11888476B2

公开(公告)日：2024-01-30

申请号：US17591093

申请日：2022-02-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daehyun Kwon ,  Hyejung Kwon ,  Hyeran Kim ,  Chisung Oh

IPC: H03K19/017 ,  H03K19/00 ,  H03K19/17736 ,  H03K19/17772

CPC classification number: H03K19/01742 ,  H03K19/0005 ,  H03K19/1774 ,  H03K19/17772

Abstract: An apparatus, a memory device, and a method for storing parameter codes with respect to asymmetric on-die-termination (ODT) are provided. The apparatus is connected to an external device via a signal line, and includes: an on-die termination (ODT) circuit set in a first ODT state; a plurality of signal pins, each of which is connected to the signal line; and an ODT control circuit configured to: identify whether a second ODT state of the external device corresponds to the first ODT state, and based on the apparatus being an asymmetric ODT in which the first ODT state and the second ODT state are different, provide an asymmetric ODT parameter code to the external device, and disable the ODT circuit when a signal is not transmitted through the signal line.