公开(公告)号：US12015335B2

公开(公告)日：2024-06-18

申请号：US17057234

申请日：2019-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mincheol Ha ,  Kwangseob Kim ,  Kihyun Kim ,  Dongzo Kim ,  Jiwon Kim ,  Jihye Kim ,  Yunjeong Noh ,  Keumsu Song ,  Changhak O ,  Kyungmin Lee ,  Hyungkoo Chung ,  Jongchul Hong ,  Yongsang Yun

IPC: H02J50/80 ,  H02J7/00 ,  H02J50/12 ,  H02J50/40 ,  H02M1/44 ,  H02M3/335

CPC classification number: H02M1/44 ,  H02J7/007182 ,  H02J50/12 ,  H02J50/402 ,  H02J50/80 ,  H02M3/33573

Abstract: Various embodiments relating to an electronic device are disclosed, and according to an embodiment, the electronic device may comprise: a plurality of coils; a first power generation circuit electrically connected to at least one of the plurality of coils; a second power generation circuit electrically connected to at least one of the plurality of coils; and a control circuit, wherein when the approach of a second external electronic device is detected while first power is provided to a first external electronic device by using a first frequency via the first power generation circuit, the control circuit allows the frequency of the second power generation circuit to be configured to a second frequency different from a first frequency in order to provide second power to the second external electronic device. Other embodiments may be possible.

公开(公告)号：US20240164101A1

公开(公告)日：2024-05-16

申请号：US18355450

申请日：2023-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiwon Kim ,  Jiyoung Kim ,  Woosung Yang ,  Dohyung Kim ,  Sukkang Sung

IPC: H10B43/27 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L2225/06541

Abstract: Disclosed are 3D semiconductor memory devices and electronic systems including the same. The 3D semiconductor memory device comprises a first substrate, a peripheral circuit structure on the first substrate, and a cell array structure on the peripheral circuit structure. The cell array structure includes a second substrate, a stack structure between the second substrate and the peripheral circuit structure and including interlayer dielectric layers and conductive patterns that are stacked alternately with the interlayer dielectric layers, vertical channel structures that include respective portions the stack structure and include vertical semiconductor patterns, respectively, and connection vias that include respective portions the second substrate and are connected to respective top surfaces of the vertical semiconductor patterns.

公开(公告)号：US20240049480A1

公开(公告)日：2024-02-08

申请号：US18120038

申请日：2023-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung Kim ,  Dohyung Kim ,  Jiwon Kim ,  Sukkang Sung

IPC: H10B80/00 ,  H10B41/27 ,  H10B43/27

CPC classification number: H10B80/00 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor device may include a first semiconductor structure including a lower substrate; and a second semiconductor structure on and bonded to the first semiconductor structure through a bonding structure. The second semiconductor structure may include: a pattern structure; an upper insulating layer on the pattern structure; a stack structure including gate electrode layers and interlayer insulating layers alternately stacked between the first semiconductor structure and the pattern structure; channel structures that extend through the stack structure; separation structures that extend through the stack structure and separate the stack structure. Each of the separation structures may include a first portion that extends through the stack structure and a second portion that extends from the first portion and extends through the pattern structure, and the second semiconductor structure further may include a spacer layer that separates the second portion of each separation structure from the pattern structure.

公开(公告)号：US20240008274A1

公开(公告)日：2024-01-04

申请号：US18178114

申请日：2023-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiwon Kim ,  Dohyung Kim ,  Jiyoung Kim ,  Sukkang Sung

IPC: H10B43/27 ,  H01L29/423 ,  H01L23/528 ,  H10B43/40 ,  H10B43/35 ,  H10B41/35 ,  H10B41/27 ,  H10B41/40

CPC classification number: H10B43/27 ,  H01L29/42328 ,  H01L29/42344 ,  H01L23/5283 ,  H10B43/40 ,  H10B43/35 ,  H10B41/35 ,  H10B41/27 ,  H10B41/40

Abstract: An integrated circuit device includes a semiconductor substrate, and a common source structure on the substrate. A vertical stack of memory cell gate electrodes is provided, which extends between the common source structure and the substrate. The vertical stack of memory cell gate electrodes includes a first erase control gate electrode, and a plurality of word lines extending between the first erase control gate electrode and the substrate. At least one channel structure is provided, which vertically penetrates through the vertical stack of memory cell gate electrodes. A source protrusion pattern is provided, which is electrically connected to the common source structure. The source protrusion pattern extends sufficiently through the vertical stack of memory cell gate electrodes that a portion of the source protrusion pattern extends opposite a sidewall of the first erase control gate electrode.

公开(公告)号：US11570486B2

公开(公告)日：2023-01-31

申请号：US17183835

申请日：2021-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiwon Kim ,  Eunji Kim

IPC: H04N21/218 ,  H04N21/222 ,  G06T19/00 ,  H04N21/44 ,  H04N13/161 ,  H04N21/226

Abstract: An example method, performed by an edge data network, of transmitting video content includes: obtaining first bearing information from an electronic device connected to the edge data network; determining second predicted bearing information based on the first bearing information; determining a second predicted partial image corresponding to the second predicted bearing information; transmitting, to the electronic device, a second predicted frame generated by encoding the second predicted partial image; obtaining, from the electronic device, second bearing information corresponding to a second partial image; comparing the second predicted bearing information to the obtained second bearing information; generating, based on a result of the comparing, a compensation frame using at least two of a first partial image corresponding to the first bearing information, the second predicted partial image, or the second partial image corresponding to the second bearing information; and transmitting the generated compensation frame to the electronic device based on the result of the comparing.

公开(公告)号：US20230014037A1

公开(公告)日：2023-01-19

申请号：US17690154

申请日：2022-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euntaek Jung ,  Jaeho Kim ,  Joonsung Kim ,  Jiwon Kim ,  Sukkang Sung ,  Sangdon Lee ,  Jong-Min Lee

IPC: H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L23/528 ,  G11C16/04

Abstract: A semiconductor device includes an electrode structure including electrodes stacked on a substrate and an insulating pattern on an uppermost electrode of the electrodes, a vertical structure that penetrates the electrode structure and is connected to the substrate, a first insulating layer on the electrode and the vertical structure, a conductive pattern that penetrates the first insulating layer and is connected to the vertical structure, an upper horizontal electrode on the conductive pattern, and an upper semiconductor pattern that penetrates the upper horizontal electrode and is connected to the conductive pattern. The conductive pattern has a first side surface on the vertical structure and a second side surface on the insulating pattern.

公开(公告)号：US11128169B2

公开(公告)日：2021-09-21

申请号：US16447113

申请日：2019-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangseob Kim ,  Keumsu Song ,  Changhak O ,  Dongzo Kim ,  Jihye Kim ,  Mincheol Ha ,  Kihyun Kim ,  Jiwon Kim ,  Yunjeong Noh ,  Kyungmin Lee ,  Hyungkoo Chung ,  Jongchul Hong ,  Yongsang Yun

IPC: H02J7/00 ,  H02J50/10 ,  H01F27/28 ,  H01F27/30

Abstract: An electronic device including a wireless charging coils, and an operating method thereof are provided. The electronic device includes a housing including a concave portion couplable to a protrusion of one or more external electronic devices, a first coil stored inside the housing, a second coil stored inside the housing, and disposed between the first coil and the concave portion, a power transmission circuit including a first connecting terminal electrically coupled to the first coil and a second connecting terminal electrically coupled to the second coil, and a control circuit. The control circuit configured to check a data packet received from the external electronic device which is in proximity to the electronic device, control to transmit first designated power to the external electronic device through the first coil wirelessly, and second designated power to the external electronic device through the second coil wirelessly by using the power transmission circuit.

公开(公告)号：US20240194266A1

公开(公告)日：2024-06-13

申请号：US18518496

申请日：2023-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiwon Kim ,  Jiyoung Kim ,  Woosung Yang ,  Dohyung Kim ,  Sukkang Sung

IPC: G11C16/08 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: G11C16/08 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506

Abstract: A semiconductor device includes a first substrate structure including a first decoder circuit region, a second decoder circuit region, and a page buffer circuit region, and a second substrate structure connected to the first substrate structure. The second substrate structure includes a first cell structure that includes first horizontally extending gate electrodes, and a second cell structure that includes second horizontally extending gate electrodes. The second cell structure is disposed below the first cell structure. A first stair structure is disposed to one side of the first and second cell structures, and a second stair structure is disposed to a second side opposite the first side. a dummy structure is disposed below the first stair structure. First contact plugs pass through the first stair structure and the first dummy structure and are respectively connected to the first gate electrodes, and second contact plugs pass through the second stair structure and are respectively connected to the second gate electrodes.

公开(公告)号：US11996352B2

公开(公告)日：2024-05-28

申请号：US17888727

申请日：2022-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woosung Yang ,  Jiyoung Kim ,  Jiwon Kim

IPC: H01L23/48 ,  H01L29/66 ,  H01L29/792 ,  H10B41/27 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

CPC classification number: H01L23/481 ,  H10B43/27

Abstract: A semiconductor device includes a substrate including a cell region and a connection region. The connection region includes a plurality of pad regions and a through electrode region. A horizontal conductive layer is on the substrate. A supporter is on the horizontal conductive layer. The supporter includes a first portion in the cell region, a second portion in the plurality of pad regions, and a third portion in the through electrode region. A connection conductive layer is between the first portion and the horizontal conductive layer. A connection mold layer is between the third portion and the horizontal conductive layer. A first buried insulation layer passing through the third portion, the connection mold layer, and the horizontal conductive layer is provided. A stacked structure is on the substrate. A through electrode passing through the first buried insulation layer is provided.

公开(公告)号：US20240023337A1

公开(公告)日：2024-01-18

申请号：US18118776

申请日：2023-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiwon Kim ,  Jiyoung Kim ,  Dohyung Kim ,  Sukkang Sung ,  Takuya Futatsuyama

IPC: H10B43/40 ,  H10B43/10 ,  H01L23/522 ,  H01L23/528 ,  H10B43/35 ,  H10B43/27

CPC classification number: H10B43/40 ,  H10B43/10 ,  H01L23/5226 ,  H01L23/5283 ,  H10B43/35 ,  H10B43/27

Abstract: Disclosed is a semiconductor device comprising a peripheral circuit structure on a first substrate, a cell array structure on the peripheral circuit structure, and a backside structure on the cell array structure. The cell array structure includes a stack structure including gate electrodes and interlayer dielectric layers that are alternately stacked, through plugs that extend in a first direction through the stack structure and each including a first surface adjacent to the backside structure and a second surface opposite to the first surface, a middle circuit structure between the stack structure and the peripheral circuit structure and connected to the peripheral circuit structure, and a connection plug connected to the middle circuit structure and the backside structure. The through plugs include a first through plug connected through the first surface to the backside structure, and a second through plug connected through the second surface to the middle circuit structure.