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公开(公告)号：US11250911B2
公开(公告)日：2022-02-15
申请号：US17196039
申请日：2021-03-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jong-chul Park , Youn-yeol Lee , Seul-bee Lee , Kyung-sub Lim
Abstract: An operating method of a storage device comprising a nonvolatile memory device comprising a first memory stack and a second memory stack, and a memory controller coupled to control the nonvolatile memory device, the operating method includes determining a first read voltage level with which a first memory cell of the first memory stack is successfully read, and performing a read operation on a second memory cell of the second memory stack using a second read voltage determined based on the first read voltage level.
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公开(公告)号：US10971210B2
公开(公告)日：2021-04-06
申请号：US16993981
申请日：2020-08-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jong-chul Park , Youn-yeol Lee , Seul-bee Lee , Kyung-sub Lim
IPC: G11C16/04 , G11C16/10 , G11C16/26 , G11C11/4074 , G11C11/409 , G11C5/06 , G11C5/02 , G11C11/408
Abstract: A nonvolatile memory device includes a memory cell region including a first metal pad, and a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory cell region includes a first memory stack comprising first memory cells vertically stacked on each other, and a second memory stack comprising second memory cells vertically stacked on each other. The peripheral circuit region includes a control logic for setting a voltage level of a second voltage applied for a second memory operation to a second memory cell of the second memory cells based on a first voltage applied to a first memory cell of the first memory cells in a first memory operation. Cell characteristics of the first memory cell are determined using the first voltage.
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公开(公告)号：US10916700B2
公开(公告)日：2021-02-09
申请号：US16513014
申请日：2019-07-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seul-ji Song , Sung-won Kim , Il-mok Park , Jong-chul Park , Ji-hyun Jeong
Abstract: A method of fabricating a memory device may include forming a first conductive line extending over a substrate in a first direction, forming a memory cell pillar on the first conductive line, and forming a second conductive line extending over the memory cell pillar in a second direction that intersects the first direction, such that the first and second conductive lines vertically overlap with the memory cell pillar interposed between the first and second conductive lines. The memory cell pillar may include a heating electrode layer and a resistive memory layer. The resistive memory layer may include a wedge memory portion and a body memory portion. The wedge memory portion may contact the heating electrode layer and may have a width that that changes with increasing distance from the heating electrode layer. The body memory portion may be connected to the wedge memory portion.
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公开(公告)号：US09985202B2
公开(公告)日：2018-05-29
申请号：US15365977
申请日：2016-12-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jeong-heon Park , Se-chung Oh , Byoung-jae Bae , Jong-chul Park
CPC classification number: H01L43/12 , H01L27/222 , H01L27/228 , H01L43/02 , H01L43/08 , H01L43/10
Abstract: A method of fabricating a memory device, the method including forming a first magnetization layer; forming a tunnel barrier layer on the first magnetization layer; forming a second magnetization layer on the tunnel barrier layer; forming a magnetic tunnel junction (MTJ) structure by patterning the first magnetization layer, the tunnel barrier layer, and the second magnetization layer; and forming a boron oxide in a sidewall of the MTJ structure by implanting boron.
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公开(公告)号：US11164631B2
公开(公告)日：2021-11-02
申请号：US17113939
申请日：2020-12-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jong-chul Park , Youn-yeol Lee , Seul-bee Lee , Kyung-sub Lim
Abstract: A nonvolatile memory device includes a first memory stack including first memory cells vertically stacked on each other, a second memory stack including memory cells vertically stacked on each other, and a control logic configured to set a voltage level of a second voltage applied for a second memory operation to one of the second memory cells in the second memory stack based on a first voltage applied to one of the first memory cells in the first memory stack in a first memory operation. The second memory stack is vertically stacked on the first memory stack. Cell characteristics of the one of the first memory cells is determined using the first voltage.
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Patent Agency Ranking
公开(公告)号：US20190341547A1
公开(公告)日：2019-11-07
申请号：US16513014
申请日：2019-07-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seul-ji Song , Sung-won Kim , Il-mok Park , Jong-chul Park , Ji-hyun Jeong
Abstract: A memory device may include a first conductive line, a second conductive line extending in a direction intersecting the first conductive line, such that the first conductive line and the second conductive line vertically overlap at a cross-point between the first conductive line and the second conductive line, and a memory cell pillar at the cross-point. The memory cell pillar may include a heating electrode layer and a resistive memory layer contacting the heating electrode layer. The resistive memory layer may include a wedge memory portion having a width that increases continuously in proportion with increasing distance from the heating electrode layer, and a body memory portion connected to the wedge memory portion such that the body memory portion and the wedge memory portion comprise an individual and continuous layer, the body memory portion having a greater width than the wedge memory portion.
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公开(公告)号：US10461127B2
公开(公告)日：2019-10-29
申请号：US15864388
申请日：2018-01-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jong-chul Park
Abstract: A variable resistance memory device including a first conductive line extending in a first direction on a substrate, a second conductive line on the first conductive line and extending in a second direction crossing the first direction, and a memory cell pillar connected to the first conductive line and the second conductive line at a crossing point therebetween and including a heating electrode layer and a variable resistance layer in contact with the heating electrode layer such that both sidewalls of the heating electrode layer are aligned with both sidewalls of the first conductive line in the first direction.
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公开(公告)号：US10885983B2
公开(公告)日：2021-01-05
申请号：US16458222
申请日：2019-07-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jong-chul Park , Youn-yeol Lee , Seul-bee Lee , Kyung-sub Lim
Abstract: A nonvolatile memory device includes a first memory stack including first memory cells vertically stacked on each other, a second memory stack including memory cells vertically stacked on each other, and a control logic configured to set a voltage level of a second voltage applied for a second memory operation to one of the second memory cells in the second memory stack based on a first voltage applied to one of the first memory cells in the first memory stack in a first memory operation. The second memory stack is vertically stacked on the first memory stack. Cell characteristics of the one of the first memory cells is determined using the first voltage.
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公开(公告)号：US10403817B2
公开(公告)日：2019-09-03
申请号：US15867951
申请日：2018-01-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seul-ji Song , Sung-won Kim , Il-mok Park , Jong-chul Park , Ji-Hyun Jeong
Abstract: A memory device may include a first conductive line, a second conductive line extending in a direction intersecting the first conductive line, such that the first conductive line and the second conductive line vertically overlap at a cross-point between the first conductive line and the second conductive line, and a memory cell pillar at the cross-point. The memory cell pillar may include a heating electrode layer and a resistive memory layer contacting the heating electrode layer. The resistive memory layer may include a wedge memory portion having a width that increases continuously in proportion with increasing distance from the heating electrode layer, and a body memory portion connected to the wedge memory portion such that the body memory portion and the wedge memory portion comprise an individual and continuous layer, the body memory portion having a greater width than the wedge memory portion.
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公开(公告)号：US20190006422A1
公开(公告)日：2019-01-03
申请号：US15864388
申请日：2018-01-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jong-chul Park
CPC classification number: H01L27/2463 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/008 , G11C2213/71 , G11C2213/73 , H01L27/2427 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/146 , H01L45/1608 , H01L45/1675
Abstract: A variable resistance memory device including a first conductive line extending in a first direction on a substrate, a second conductive line on the first conductive line and extending in a second direction crossing the first direction, and a memory cell pillar connected to the first conductive line and the second conductive line at a crossing point therebetween and including a heating electrode layer and a variable resistance layer in contact with the heating electrode layer such that both sidewalls of the heating electrode layer are aligned with both sidewalls of the first conductive line in the first direction.
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