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公开(公告)号：US11869571B2
公开(公告)日：2024-01-09
申请号：US17899141
申请日：2022-08-30
发明人： Youngcheon Kwon , Jaeyoun Youn , Namsung Kim , Kyomin Sohn , Seongil O , Sukhan Lee
IPC分类号： G11C11/406 , G11C11/408 , G11C7/10 , G11C11/4076
CPC分类号： G11C11/40618 , G11C7/1045 , G11C7/1048 , G11C11/408 , G11C11/4076 , G11C11/40622
摘要： A memory device including: a plurality of pins for receiving control signals from an external device; a first bank having first memory cells, wherein the first bank is activated in a first operation mode and a second operation mode; a second bank having second memory cells, wherein the second bank is deactivated in the first operation mode and activated in the second operation mode; a processing unit configured to perform an operation on first data, output from the first memory cells, and second data, output from the second memory cells, in the second operation mode; and a processing-in-memory (PIM) mode controller configured to select mode information, indicating one of the first operation mode and the second operation mode, in response to the control signals and to control at least one memory parameter, at least one mode register set (MRS) value, or a refresh mode according to the mode information.
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2.发明授权公开(公告)号：US11335392B2
公开(公告)日：2022-05-17
申请号：US16903055
申请日：2020-06-16
发明人： Youngcheon Kwon , Sanghyuk Kwon , Kyomin Sohn , Jaeyoun Youn , Haesuk Lee
IPC分类号： G11C11/406 , G11C11/408
摘要： A memory device according to some aspects of the inventive concepts includes a memory cell array including a plurality of banks, at least one Processing Element (PE) connected to at least one bank selected from the plurality of banks, and a control logic configured to control an active operation in which wordlines included in each of the plurality of banks is activated, and configured to control a refresh operation in which at least one bank is refreshed, based on a PE enable signal configured to selectively enable the at least one PE.
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公开(公告)号：US20230214124A1
公开(公告)日：2023-07-06
申请号：US17934691
申请日：2022-09-23
发明人： Shinhaeng Kang , Sukhan Lee , Kyomin Sohn
IPC分类号： G06F3/06
CPC分类号： G06F3/0613 , G06F3/0629 , G06F3/0673
摘要： A memory device includes a memory bank including a plurality of banks that comprise memory cells, and a PIM (processing in memory) circuit including a plurality of PIM blocks, each of the PIM blocks including an arithmetic logic unit (ALU) configured to perform an arithmetic operation using internal data acquired from at least one of the plurality of banks or an address generating unit. The plurality of PIM blocks include a first PIM block allocated to at least one first bank and a second PIM block allocated to at least one second bank. The address generating unit of the first PIM block is configured to generate a first internal row address for the at least one first bank, and the address generating unit of the second PIM block is configured to generate a second internal row address for the at least one second bank.
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公开(公告)号：US20230128183A1
公开(公告)日：2023-04-27
申请号：US17938789
申请日：2022-10-07
发明人： Shinhaeng Kang , Sukhan Lee , Hweesoo Kim , Kyomin Sohn
IPC分类号： G06F3/06
摘要： A memory device supporting a processing-in-memory (PIM) protocol includes a mode register set (MRS) configured to store a first parameter code and a second parameter code regarding the PIM protocol in a first register and a second register, respectively. The first parameter code includes a PIM protocol change code indicating whether a PIM protocol change related to an old version PIM protocol is supported, and the second parameter code includes a PIM protocol code for setting a current operation PIM protocol from among a plurality of PIM protocols. The memory device further includes a PIM circuit configured to perform an internal processing operation based on the current operation PIM protocol.
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公开(公告)号：US11301399B2
公开(公告)日：2022-04-12
申请号：US16934497
申请日：2020-07-21
发明人： Sang-Hyuk Kwon , Nam Sung Kim , Kyomin Sohn , Jaeyoun Youn
IPC分类号： G06F13/38 , G06F13/16 , H01L25/065 , G11C8/10 , G11C7/10
摘要： A memory device includes a buffer die configured to receive a first broadcast command and a second broadcast command from an external device; and a plurality of core dies stacked on the buffer die. The plurality of core dies include: a first core die including a first processing circuit, a first memory cell array, a first command decoder configured to decode the first broadcast command, and a first data input/output circuit configured to output data of the first memory cell array to a common data input/output bus under control of the first command decoder; and a second core die including a second processing circuit, a second memory cell array, a second command decoder configured to decode the second broadcast command, and a second data input/output circuit configured to receive the data of the first memory cell array through the common data input/output bus under control of the second command decoder.
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公开(公告)号：US11152053B2
公开(公告)日：2021-10-19
申请号：US16994796
申请日：2020-08-17
发明人： Sang-Hyuk Kwon , Nam Sung Kim , Kyomin Sohn , Seongil O , Haesuk Lee
IPC分类号： G11C11/408 , G11C11/4074 , G11C11/4096 , G11C11/4094 , G11C7/10 , G11C11/406 , G11C8/12 , G11C11/4076
摘要： A memory device includes a memory cell array including a plurality of banks each including a plurality of memory cells connected to a plurality of word lines, and a row decoder block connected to the plurality of banks. In a first operation mode, the row decoder block receives a first row address and a first bank address together with an activation command and activates a word line selected by the first row address from among the plurality of word lines of a bank selected by the first bank address from among the plurality of banks. In a second operation mode, the row decoder block receives a second row address and a second bank address together with the activation command and activates a word line selected by the second row address from among the plurality of word lines of each of at least two banks of the plurality of banks.
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公开(公告)号：US20240281323A1
公开(公告)日：2024-08-22
申请号：US18469894
申请日：2023-09-19
发明人： Myungkyu Lee , Seongmuk Kang , Jiho Kim , Kijun Lee , Kyomin Sohn
IPC分类号： G06F11/10
CPC分类号： G06F11/1044
摘要： A memory controller including a processor and configured to control a memory module including a plurality of data chips and at least one parity chip includes an error correction code (ECC) engine, the ECC engine including an ECC decoder to correct Q symbols errors in a codeword set read from the memory module, Q is a maximum natural number equal to or less than P and P is a natural number equal to or greater than four. The ECC decoder is configured to generate a syndrome including first through P-th syndrome symbols based on the read codeword set by using a parity check matrix and to perform a first ECC decoding to correct a single symbol error in the read codeword set based on the first syndrome symbol and a selected syndrome symbol corresponding to one of the second through P-th syndrome symbols.
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公开(公告)号：US20240161850A1
公开(公告)日：2024-05-16
申请号：US18362130
申请日：2023-07-31
发明人： Byeongho Kim , Shinhaeng Kang , Suk Han Lee , Hweesoo Kim , Kyomin Sohn
CPC分类号： G11C29/18 , G11C29/1201 , G11C2029/1202 , G11C2029/1204
摘要： A memory device which includes a plurality of memory chips. Each of the plurality of memory chips includes a plurality of memory banks and a logic circuit performing a read operation on data stored in the plurality of memory banks based on a first command and a first address received from a host. When a PIM instruction set is stored before the first command and the first address are received, the logic circuit is configured to perform a PIM command execution operation. When an error associated with the PIM command execution operation occurs, the logic circuit is configured to generate error data and record the error data at the log register through the first channels. The logic circuit is configured to output event data indicating an existence of the error data to the host in a first operation mode. The logic circuit is configured to output the error data to the host in a second operation mode.
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公开(公告)号：US11860803B2
公开(公告)日：2024-01-02
申请号：US17685987
申请日：2022-03-03
发明人： Sang-Hyuk Kwon , Nam Sung Kim , Kyomin Sohn , Jaeyoun Youn
IPC分类号： G06F13/38 , G06F13/16 , H01L25/065 , G11C8/10 , G11C7/10
CPC分类号： G06F13/1668 , H01L25/0657 , G11C7/10 , G11C8/10 , H01L2225/06541
摘要： A memory device includes a buffer die configured to receive a first broadcast command and a second broadcast command from an external device; and a plurality of core dies stacked on the buffer die. The plurality of core dies include: a first core die including a first processing circuit, a first memory cell array, a first command decoder configured to decode the first broadcast command, and a first data input/output circuit configured to output data of the first memory cell array to a common data input/output bus under control of the first command decoder; and a second core die including a second processing circuit, a second memory cell array, a second command decoder configured to decode the second broadcast command, and a second data input/output circuit configured to receive the data of the first memory cell array through the common data input/output bus under control of the second command decoder.
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公开(公告)号：US11763876B2
公开(公告)日：2023-09-19
申请号：US17475479
申请日：2021-09-15
发明人： Sang-Hyuk Kwon , Nam Sung Kim , Kyomin Sohn , Seongil O , Haesuk Lee
IPC分类号： G11C8/12 , G11C11/408 , G11C11/4074 , G11C11/4096 , G11C11/4094 , G11C7/10 , G11C11/406 , G11C11/4076
CPC分类号： G11C11/4087 , G11C7/1006 , G11C8/12 , G11C11/4074 , G11C11/4076 , G11C11/4085 , G11C11/4094 , G11C11/4096 , G11C11/40618
摘要： A memory device includes a memory cell array including a plurality of banks each including a plurality of memory cells connected to a plurality of word lines, and a row decoder block connected to the plurality of banks. In a first operation mode, the row decoder block receives a first row address and a first bank address together with an activation command and activates a word line selected by the first row address from among the plurality of word lines of a bank selected by the first bank address from among the plurality of banks. In a second operation mode, the row decoder block receives a second row address and a second bank address together with the activation command and activates a word line selected by the second row address from among the plurality of word lines of each of at least two banks of the plurality of banks.
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