公开(公告)号：US20250036521A1

公开(公告)日：2025-01-30

申请号：US18770435

申请日：2024-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungkyu Lee ,  Seongmuk Kang ,  Jae-Gon Lee ,  Kyomin Sohn ,  Yeonggeol Song ,  Kijun Lee

IPC: G06F11/10

Abstract: An example CXL (Compute eXpress Link)-based memory module includes a memory device and a controller. The memory device includes a plurality of volatile memory cells and stores data or reads the stored data. The controller communicates with a host device through a CXL interface and controls the memory device. The controller includes an error correction code (ECC) circuit that generates a first codeword by adding a parity vector generated based on Reed-Solomon encoding to data received from the host device, an error injecting circuit that generates an error symbol and generates a second codeword by injecting the error symbol into at least a portion of the first codeword, and a memory device interface that controls the memory device such that the second codeword where the error symbol is injected is stored in the memory device. The controller determines a number of error symbols to be injected into the second codeword.

公开(公告)号：US12182409B2

公开(公告)日：2024-12-31

申请号：US17938789

申请日：2022-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shinhaeng Kang ,  Sukhan Lee ,  Hweesoo Kim ,  Kyomin Sohn

IPC: G06F3/06

Abstract: A memory device supporting a processing-in-memory (PIM) protocol includes a mode register set (MRS) configured to store a first parameter code and a second parameter code regarding the PIM protocol in a first register and a second register, respectively. The first parameter code includes a PIM protocol change code indicating whether a PIM protocol change related to an old version PIM protocol is supported, and the second parameter code includes a PIM protocol code for setting a current operation PIM protocol from among a plurality of PIM protocols. The memory device further includes a PIM circuit configured to perform an internal processing operation based on the current operation PIM protocol.

公开(公告)号：US11869571B2

公开(公告)日：2024-01-09

申请号：US17899141

申请日：2022-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngcheon Kwon ,  Jaeyoun Youn ,  Namsung Kim ,  Kyomin Sohn ,  Seongil O ,  Sukhan Lee

IPC: G11C11/406 ,  G11C11/408 ,  G11C7/10 ,  G11C11/4076

CPC classification number: G11C11/40618 ,  G11C7/1045 ,  G11C7/1048 ,  G11C11/408 ,  G11C11/4076 ,  G11C11/40622

Abstract: A memory device including: a plurality of pins for receiving control signals from an external device; a first bank having first memory cells, wherein the first bank is activated in a first operation mode and a second operation mode; a second bank having second memory cells, wherein the second bank is deactivated in the first operation mode and activated in the second operation mode; a processing unit configured to perform an operation on first data, output from the first memory cells, and second data, output from the second memory cells, in the second operation mode; and a processing-in-memory (PIM) mode controller configured to select mode information, indicating one of the first operation mode and the second operation mode, in response to the control signals and to control at least one memory parameter, at least one mode register set (MRS) value, or a refresh mode according to the mode information.

公开(公告)号：US11335392B2

公开(公告)日：2022-05-17

申请号：US16903055

申请日：2020-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngcheon Kwon ,  Sanghyuk Kwon ,  Kyomin Sohn ,  Jaeyoun Youn ,  Haesuk Lee

IPC: G11C11/406 ,  G11C11/408

Abstract: A memory device according to some aspects of the inventive concepts includes a memory cell array including a plurality of banks, at least one Processing Element (PE) connected to at least one bank selected from the plurality of banks, and a control logic configured to control an active operation in which wordlines included in each of the plurality of banks is activated, and configured to control a refresh operation in which at least one bank is refreshed, based on a PE enable signal configured to selectively enable the at least one PE.

公开(公告)号：US20250104791A1

公开(公告)日：2025-03-27

申请号：US18668224

申请日：2024-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaewon Park ,  Jaehoon Lee ,  Kyomin Sohn

IPC: G11C29/18

Abstract: A memory device includes: a built-in self-test circuit configured to select a first target bank and a second target bank for each of a plurality of row addresses such that each of a plurality of memory banks is selected as the first target bank and the second target bank at least once, and to perform parallel tests on the first and second target banks for each of the plurality of row addresses; a comparator configured to compare first data output from the first target bank and second data output from the second target bank, and to output a fail signal according to a comparison result thereof; and a built-in analysis circuit configured to update a fail bank table indicating fail information of each of the plurality of memory banks, in response to the fail signal, and to determine a defective bank by referring to the fail bank table.

公开(公告)号：US20240385925A1

公开(公告)日：2024-11-21

申请号：US18543737

申请日：2023-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungkyu Lee ,  Seongmuk Kang ,  Daehyun Kim ,  Jiho Kim ,  Kyomin Sohn ,  Kijun Lee ,  Sunghye Cho

IPC: G06F11/10 ,  G06F11/00 ,  G06F11/07

Abstract: A memory system includes a plurality of volatile memory devices and a memory controller. The memory controller includes a plurality of volatile memory devices; and a memory controller configured to control the plurality of volatile memory devices, wherein the memory controller includes: a host interface configured to communicate with a host device based on a Compute eXpress Link (CXL) communication protocol; an error correction level (ECL) manager configured to receive cache line data from the host device through the host interface, and output an error correction code (ECC) control signal indicating one of a first correction level and a second correction level being error correction levels based on cell reliability information and data reliability request information which are associated with the cache line data; and an ECC engine configured to, based on the ECC control signal indicating the first correction level, generate first parity symbols associated with the cache line data, and based on the ECC control signal indicating the second correction level, generate additional parity symbols.

公开(公告)号：US20230214124A1

公开(公告)日：2023-07-06

申请号：US17934691

申请日：2022-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhaeng Kang ,  Sukhan Lee ,  Kyomin Sohn

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0629 ,  G06F3/0673

Abstract: A memory device includes a memory bank including a plurality of banks that comprise memory cells, and a PIM (processing in memory) circuit including a plurality of PIM blocks, each of the PIM blocks including an arithmetic logic unit (ALU) configured to perform an arithmetic operation using internal data acquired from at least one of the plurality of banks or an address generating unit. The plurality of PIM blocks include a first PIM block allocated to at least one first bank and a second PIM block allocated to at least one second bank. The address generating unit of the first PIM block is configured to generate a first internal row address for the at least one first bank, and the address generating unit of the second PIM block is configured to generate a second internal row address for the at least one second bank.

公开(公告)号：US20230128183A1

公开(公告)日：2023-04-27

申请号：US17938789

申请日：2022-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shinhaeng Kang ,  Sukhan Lee ,  Hweesoo Kim ,  Kyomin Sohn

IPC: G06F3/06

Abstract: A memory device supporting a processing-in-memory (PIM) protocol includes a mode register set (MRS) configured to store a first parameter code and a second parameter code regarding the PIM protocol in a first register and a second register, respectively. The first parameter code includes a PIM protocol change code indicating whether a PIM protocol change related to an old version PIM protocol is supported, and the second parameter code includes a PIM protocol code for setting a current operation PIM protocol from among a plurality of PIM protocols. The memory device further includes a PIM circuit configured to perform an internal processing operation based on the current operation PIM protocol.

公开(公告)号：US11301399B2

公开(公告)日：2022-04-12

申请号：US16934497

申请日：2020-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Hyuk Kwon ,  Nam Sung Kim ,  Kyomin Sohn ,  Jaeyoun Youn

IPC: G06F13/38 ,  G06F13/16 ,  H01L25/065 ,  G11C8/10 ,  G11C7/10

Abstract: A memory device includes a buffer die configured to receive a first broadcast command and a second broadcast command from an external device; and a plurality of core dies stacked on the buffer die. The plurality of core dies include: a first core die including a first processing circuit, a first memory cell array, a first command decoder configured to decode the first broadcast command, and a first data input/output circuit configured to output data of the first memory cell array to a common data input/output bus under control of the first command decoder; and a second core die including a second processing circuit, a second memory cell array, a second command decoder configured to decode the second broadcast command, and a second data input/output circuit configured to receive the data of the first memory cell array through the common data input/output bus under control of the second command decoder.

公开(公告)号：US11152053B2

公开(公告)日：2021-10-19

申请号：US16994796

申请日：2020-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hyuk Kwon ,  Nam Sung Kim ,  Kyomin Sohn ,  Seongil O ,  Haesuk Lee

IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/4094 ,  G11C7/10 ,  G11C11/406 ,  G11C8/12 ,  G11C11/4076

Abstract: A memory device includes a memory cell array including a plurality of banks each including a plurality of memory cells connected to a plurality of word lines, and a row decoder block connected to the plurality of banks. In a first operation mode, the row decoder block receives a first row address and a first bank address together with an activation command and activates a word line selected by the first row address from among the plurality of word lines of a bank selected by the first bank address from among the plurality of banks. In a second operation mode, the row decoder block receives a second row address and a second bank address together with the activation command and activates a word line selected by the second row address from among the plurality of word lines of each of at least two banks of the plurality of banks.