公开(公告)号：US08912611B2

公开(公告)日：2014-12-16

申请号：US14190346

申请日：2014-02-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： WeonHong Kim ,  Dae-Kwon Joo ,  Hajin Lim ,  Jinho Do ,  Kyungil Hong ,  Moonkyun Song

IPC: H01L21/02 ,  H01L29/51 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/512 ,  H01L21/28202 ,  H01L21/28255 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: A method of fabricating a semiconductor device includes forming a lower interfacial layer on a semiconductor layer, the lower interfacial layer being a nitride layer, forming an intermediate interfacial layer on the lower interfacial layer, the intermediate interfacial layer being an oxide layer, and forming a high-k dielectric layer on the intermediate interfacial layer. The high-k dielectric layer has a dielectric constant that is higher than dielectric constants of the lower interfacial layer and the intermediate interfacial layer.

Abstract translation: 制造半导体器件的方法包括在半导体层上形成下界面层，下界面层为氮化物层，在下界面层上形成中间界面层，中间界面层为氧化物层，形成 中间界面层上的高k电介质层。 高k电介质层的介电常数高于下界面层和中间界面层的介电常数。

公开(公告)号：US12262641B2

公开(公告)日：2025-03-25

申请号：US17466246

申请日：2021-09-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungil Hong ,  Jungmin Lee ,  Younghyun Kim ,  Junghwan Park ,  Heeju Shin ,  Se Chung Oh

IPC: H10N50/10 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A method of fabricating a magnetic memory device comprises forming, on a substrate, a data storage structure including a bottom electrode, a magnetic tunnel junction pattern, and a top electrode, forming a first capping dielectric layer conformally covering lateral and top surfaces of the data storage structure, and forming a second capping dielectric layer on the first capping dielectric layer. The forming the first capping dielectric layer is performed by PECVD in which a first source gas, a first reaction gas, and a first purging gas are supplied. The forming the second capping dielectric layer Is performed by PECVD in which a second source gas, a second reaction gas, and a second purging gas are supplied. The first and second reaction gases are different from each other. The first and second purging gases are different from each other.

公开(公告)号：US11495736B2

公开(公告)日：2022-11-08

申请号：US16793336

申请日：2020-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungil Hong ,  Younghyun Kim ,  Junghwan Park ,  Sechung Oh ,  Jungmin Lee

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01L27/1159 ,  H01L43/08 ,  H01L27/24

Abstract: A semiconductor device includes a plurality of magnetic tunnel junction (MTJ) structures in an interlayer insulating layer on a substrate. A blocking layer is on the interlayer insulating layer and the plurality of MTJ structures. An upper insulating layer is on the blocking layer. An upper interconnection is on the upper insulating layer. An upper plug is connected to the upper interconnection and a corresponding one of the plurality of MTJ structures and extends into the upper insulating layer and the blocking layer. The blocking layer includes a material having a higher absorbance constant than the upper insulating layer.

公开(公告)号：US11329219B2

公开(公告)日：2022-05-10

申请号：US16840741

申请日：2020-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmin Lee ,  Younghyun Kim ,  Junghwan Park ,  Sechung Oh ,  Kyungil Hong

IPC: H01L43/12 ,  H01L27/22 ,  H01L21/02 ,  H01L43/08

Abstract: In a method of manufacturing a magnetoresistive random access memory, a memory structure may be formed on a substrate. The memory structure may include a lower electrode, a magnetic tunnel junction (MTJ) structure, and an upper electrode sequentially stacked. A protection layer including silicon nitride may be formed to cover a surface of the memory structure. The protection layer may be formed by a chemical vapor deposition process using plasma and introducing deposition gases including a silicon source gas, a nitrogen source gas containing no hydrogen and a dissociation gas. Damages of the MTJ structure may be decreased during forming the protection layer. Thus, the MRAM may have improved characteristics.

公开(公告)号：US20230180625A1

公开(公告)日：2023-06-08

申请号：US17817441

申请日：2022-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonmyoung Lee ,  Junghwan Park ,  Jeong-Heon Park ,  Kyungil Hong

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L43/12

Abstract: A magnetic memory device includes a first magnetic pattern and a second magnetic pattern that are sequentially stacked on a substrate, a tunnel barrier pattern between the first magnetic pattern and the second magnetic pattern, a lower electrode between the substrate and the first magnetic pattern, a blocking pattern between the lower electrode and the first magnetic pattern, a metal oxide pattern between the blocking pattern and the first magnetic pattern, and a buffer pattern between the metal oxide pattern and the first magnetic pattern. The lower electrode, the blocking pattern, the metal oxide pattern, and the buffer pattern include first, second, third, and fourth non-magnetic metals, respectively. The metal oxide pattern has an amorphous phase.

公开(公告)号：US20210043833A1

公开(公告)日：2021-02-11

申请号：US16840741

申请日：2020-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmin Lee ,  Younghyun Kim ,  Junghwan Park ,  Sechung Oh ,  Kyungil Hong

IPC: H01L43/12 ,  H01L43/08 ,  H01L21/02 ,  H01L27/22

Abstract: In a method of manufacturing a magnetoresistive random access memory, a memory structure may be formed on a substrate. The memory structure may include a lower electrode, a magnetic tunnel junction (MTJ) structure, and an upper electrode sequentially stacked. A protection layer including silicon nitride may be formed to cover a surface of the memory structure. The protection layer may be formed by a chemical vapor deposition process using plasma and introducing deposition gases including a silicon source gas, a nitrogen source gas containing no hydrogen and a dissociation gas. Damages of the MTJ structure may be decreased during forming the protection layer. Thus, the MRAM may have improved characteristics.

公开(公告)号：US11683992B2

公开(公告)日：2023-06-20

申请号：US17134456

申请日：2020-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungjong Jeong ,  Ki Woong Kim ,  Younghyun Kim ,  Junghwan Park ,  Byoungjae Bae ,  Se Chung Oh ,  Jungmin Lee ,  Kyungil Hong

IPC: H10N50/80 ,  H10N50/01 ,  H10B61/00 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22

CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L43/12

Abstract: A magnetic memory device may include an interlayer insulating layer on a substrate, a bottom electrode contact disposed in the interlayer insulating layer, and a magnetic tunnel junction pattern on the bottom electrode contact. The bottom electrode contact may include a second region and a first region, which are sequentially disposed in a first direction perpendicular to a top surface of the substrate so that the second region is between the first region and the top surface of the substrate. A first width of the first region may be smaller than a second width of the second region, when measured in a second direction parallel to the top surface of the substrate.

公开(公告)号：US11600662B2

公开(公告)日：2023-03-07

申请号：US17582628

申请日：2022-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghwan Park ,  Younghyun Kim ,  Se Chung Oh ,  Jungmin Lee ,  Kyungil Hong

IPC: H01L27/22 ,  H01L43/10 ,  H01L43/08 ,  H01L43/12 ,  H01L43/02 ,  H01L43/04 ,  H01L43/06

Abstract: Data storage devices are provided. A data storage device includes a memory transistor on a substrate and a data storage structure electrically connected to the memory transistor. The data storage structure includes a magnetic tunnel junction pattern and a top electrode on the magnetic tunnel junction pattern. The top electrode includes a first top electrode and a second top electrode on the first top electrode, and the first and second top electrodes include the same metal nitride. The first top electrode includes first crystal grains of the metal nitride, and the second top electrode includes second crystal grains of the metal nitride. In a section of the top electrode, the number of the first crystal grains per a unit length is greater than the number of the second crystal grains per the unit length.

公开(公告)号：US11271037B2

公开(公告)日：2022-03-08

申请号：US16803574

申请日：2020-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghwan Park ,  Younghyun Kim ,  Se Chung Oh ,  Jungmin Lee ,  Kyungil Hong

IPC: H01L27/22 ,  H01L43/10 ,  H01L43/08 ,  H01L43/12 ,  H01L43/02

Abstract: Data storage devices are provided. A data storage device includes a memory transistor on a substrate and a data storage structure electrically connected to the memory transistor. The data storage structure includes a magnetic tunnel junction pattern and a top electrode on the magnetic tunnel junction pattern. The top electrode includes a first top electrode and a second top electrode on the first top electrode, and the first and second top electrodes include the same metal nitride. The first top electrode includes first crystal grains of the metal nitride, and the second top electrode includes second crystal grains of the metal nitride. In a section of the top electrode, the number of the first crystal grains per a unit length is greater than the number of the second crystal grains per the unit length.

公开(公告)号：US09142461B2

公开(公告)日：2015-09-22

申请号：US14289076

申请日：2014-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinho Do ,  Hajin Lim ,  WeonHong Kim ,  Kyungil Hong ,  Moonkyun Song

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L21/823462 ,  H01L21/26506 ,  H01L21/28185 ,  H01L21/2822 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A substrate including an NMOS transistor region and a PMOS transistor region is prepared. A silicon-germanium layer is formed on the PMOS transistor region. Nitrogen atoms are injected in an upper portion of the silicon-germanium layer. A first gate dielectric layer is formed on the NMOS transistor region and the PMOS transistor region. The nitrogen atoms are injected into the upper portion of the silicon-germanium layer before forming the first gate dielectric layer.

Abstract translation: 准备包括NMOS晶体管区域和PMOS晶体管区域的衬底。 在PMOS晶体管区域上形成硅 - 锗层。 氮原子注入硅 - 锗层的上部。 在NMOS晶体管区域和PMOS晶体管区域上形成第一栅极电介质层。 在形成第一栅极电介质层之前，将氮原子注入硅 - 锗层的上部。