公开(公告)号：US20230066186A1

公开(公告)日：2023-03-02

申请号：US17893274

申请日：2022-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangmin Kang ,  Hyungjoon Kim ,  Sangsoo Lee ,  Woojin Jang ,  Dongsung Choi

IPC: H01L27/11582 ,  G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: A semiconductor device and a method of manufacturing the same. The method may include: forming a mold stack that includes a plurality of insulating layers alternately arranged with a plurality of sacrificial layers; forming a preliminary pad portion by sequentially patterning the mold stack; forming a cell contact hole that extends through the preliminary pad portion and the sacrificial layer portions; forming a first extension portion and a plurality of second extension portions by laterally expanding the preliminary pad portion and the sacrificial layer portions; forming a first insulating liner and a sacrificial ring pattern in the first extension portion; forming an oxide liner and an insulating ring pattern in the second extension portions; forming a sacrificial plug within the cell contact hole; and replacing the sacrificial layers with gate electrodes and replacing the preliminary pad portion, the first insulating liner, and the sacrificial ring pattern with a pad portion.

公开(公告)号：US20230292491A1

公开(公告)日：2023-09-14

申请号：US18090043

申请日：2022-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungwook Park ,  Sangmin Kang ,  Yoongoo Kang ,  Changwoo Seo ,  Suyoun Song ,  Dain Lee

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/34 ,  H10B12/482 ,  H10B12/0335

Abstract: A semiconductor device may include contact plug structures on a substrate, and an insulation structure filling a space between the contact plug structures to insulate the contact plug structures from each other. The contact plug structures may be spaced apart from each other in a first direction. The insulation structure may include a first insulation pattern and a second insulation pattern. The second insulation pattern may include an insulation material having an etch selectivity with respect to silicon oxide. The first insulation pattern may contact a portion of sidewalls of the second insulation pattern and a portion of sidewalls of the contact plug structure. The first insulation pattern may include a material having a band gap higher than a band gap of the second insulation pattern.

公开(公告)号：US20230087072A1

公开(公告)日：2023-03-23

申请号：US17736173

申请日：2022-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangmin Kang ,  Hyungjoon Kim ,  WooJin Jang

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: A method of fabricating an integrated circuit device includes forming on a semiconductor substrate a mold stack that includes a plurality of insulating layers and a plurality of mold layers alternately arranged. A mask pattern including an opening is formed on the mold stack. A channel hole is formed by removing the mold stack exposed through the opening. A sacrificial film is formed on a lateral wall of the mold stack exposed through the channel hole. An oxidation process is performed on the sacrificial film and the mold stack to convert the sacrificial film to a sacrificial oxide film. An etching process is performed to remove the sacrificial oxide film.

公开(公告)号：US11594548B2

公开(公告)日：2023-02-28

申请号：US17029269

申请日：2020-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangmin Kang ,  Hanvit Yang

IPC: H01L27/11575 ,  H01L23/48 ,  H01L23/528 ,  H01L27/11582 ,  H01L21/768 ,  H01L27/11573 ,  H01L23/50

Abstract: A semiconductor device includes a substrate, a lower structure on the substrate, the lower structure including a first wiring structure, a second wiring structure, and a lower insulating structure covering the first and second wiring structures, a first pattern layer including a plate portion and a via portion, the plate portion being on the lower insulating structure and the via portion extending into the lower insulating structure from a lower portion of the plate portion and overlapping the first wiring structure, a graphene-like carbon material layer in contact with the via portion and the first wiring structure between the via portion and the first wiring structure, gate layers stacked in a vertical direction perpendicular to an upper surface of the substrate and spaced apart from each other on the first pattern layer, and a memory vertical structure penetrating through the gate layers in the vertical direction.

公开(公告)号：US20210384200A1

公开(公告)日：2021-12-09

申请号：US17173179

申请日：2021-02-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangmin Kang ,  Hanvit Yang ,  Jihoon Choi

IPC: H01L27/1157 ,  H01L27/11582

Abstract: A mold including insulation layers and sacrificial layers is formed on a substrate. A channel hole is formed through the mold. A first deposition process is performed using a first precursor including silane and a second precursor including silane and a halogen element to form a first preliminary blocking layer on a sidewall of the channel hole. A second deposition process is performed using the first precursor to form a second preliminary blocking layer on the sidewall of the channel hole. The first and second preliminary blocking layers form a third preliminary blocking layer. An oxidation process is performed on the third preliminary blocking layer to transform the third preliminary blocking into a first blocking layer. A charge storage layer, a tunnel insulation layer, and a channel layer are formed on the first blocking layer. The sacrificial layer is replaced with a gate electrode.

公开(公告)号：US20240243183A1

公开(公告)日：2024-07-18

申请号：US18462724

申请日：2023-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangmin Kang ,  Sunggil Kim ,  Kyungwook Park

IPC: H01L29/45 ,  H01L23/00 ,  H01L29/417

CPC classification number: H01L29/456 ,  H01L24/08 ,  H01L29/41741 ,  H10B43/27

Abstract: A semiconductor device includes: a first substrate structure including a first substrate, circuit devices, and first bonding pads; and a second substrate structure connected to the first substrate structure. The second substrate structure includes: a source structure; gate electrodes stacked and spaced apart from each other below the source structure in a first direction; first contact plugs electrically connected to the gate electrodes and extending in the first direction; a second contact plug extending in the first direction in an external side of the gate electrodes and electrically connected to the source structure through an upper end; a diffusion barrier between the second contact plug and the source structure, wherein a level of a lower end thereof is higher than a level of an uppermost surface of the gate electrodes; and second bonding pads below the gate electrodes and connected to the first bonding pads.

公开(公告)号：US20230328985A1

公开(公告)日：2023-10-12

申请号：US18062251

申请日：2022-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangmin Kang ,  Bio Kim ,  Kyungwook Park

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/35 ,  H10B41/40 ,  H10B41/27 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H01L23/522 ,  H01L23/528 ,  G11C5/06

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  G11C5/06 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11565

Abstract: A semiconductor device includes a peripheral circuit structure including: a first substrate, circuit devices on the first substrate, a lower wiring structure electrically connected to the circuit devices, a lower insulating layer covering the lower wiring structure, and a diffusion barrier layer on the lower insulating layer; and a memory cell structure including a second substrate including first and second regions on the peripheral circuit structure, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the second substrate in the first region and extending in a second direction perpendicular to the first direction to form a staircase shape in the second region, and channel structures penetrating the gate electrodes in the first direction and each including a channel layer. The diffusion barrier layer includes a first material layer having a hydrogen permeability lower than a hydrogen permeability of silicon nitride.

公开(公告)号：US11744077B2

公开(公告)日：2023-08-29

申请号：US17173179

申请日：2021-02-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangmin Kang ,  Hanvit Yang ,  Jihoon Choi

IPC: H10B43/27 ,  H10B43/35

CPC classification number: H10B43/35 ,  H10B43/27

Abstract: A mold including insulation layers and sacrificial layers is formed on a substrate. A channel hole is formed through the mold. A first deposition process is performed using a first precursor including silane and a second precursor including silane and a halogen element to form a first preliminary blocking layer on a sidewall of the channel hole. A second deposition process is performed using the first precursor to form a second preliminary blocking layer on the sidewall of the channel hole. The first and second preliminary blocking layers form a third preliminary blocking layer. An oxidation process is performed on the third preliminary blocking layer to transform the third preliminary blocking into a first blocking layer. A charge storage layer, a tunnel insulation layer, and a channel layer are formed on the first blocking layer. The sacrificial layer is replaced with a gate electrode.

公开(公告)号：US20230164999A1

公开(公告)日：2023-05-25

申请号：US17962577

申请日：2022-10-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangmin Kang ,  Junghwan Kim ,  Hyungjoon Kim ,  Jihoon Choi

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524 ,  H01L23/5283

Abstract: A semiconductor device includes gate electrodes on a substrate and a memory channel structure extending through the gate electrodes. The gate electrodes are spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate. The memory channel structure extends in the vertical direction on the substrate. The memory channel structure includes a first filling pattern extending in the vertical direction, a channel on a sidewall of the first filling pattern, and a charge storage structure on a sidewall of the channel. The first filling pattern includes a material having a thermal conductivity equal to or more than about 100 W/m·K at a temperature of about 25° C.